• Korean Journal of Remote Sensing
• /
• v.23 no.1
• /
• pp.7-14
• /
• 2007

Atmospheric correction is one of critical procedures to extract quantitative information related to biophysical variables from hyperspectral imagery. Most atmospheric correction algorithms developed for hyperspectral data have been based upon atmospheric radiative transfer (RT) codes, such as MODTRAN. Because of the difficulty in acquisition of atmospheric data at the time of image capture, the complexity of RT model, and large volume of hyperspectral data, atmospheric correction can be very difficult and time-consuming processing. In this study, we attempted to develop an efficient method for the atmospheric correction of EO-1 Hyperion data. This method uses the pre-calculated look-up-table (LUT) for fast and simple processing. The pre-calculated LUT was generated by successive running of MODTRAN model with several input parameters related to solar and sensor geometry, radiometric specification of sensor, and atmospheric condition. Atmospheric water vapour contents image was generated directly from a few absorption bands of Hyperion data themselves and used one of input parameters. This new atmospheric correction method was tested on the Hyperion data acquired on June 3, 2001 over Seoul area. Reflectance spectra of several known targets corresponded with the typical pattern of spectral reflectance on the atmospherically corrected Hyperion image, although further improvement to reduce sensor noise is necessary.

• Korean Journal of Remote Sensing
• /
• v.19 no.4
• /
• pp.319-328
• /
• 2003

The automatic analysis of high-resolution satellite image is important in cartography, surveillance, exploiting resources etc. However, the automatic analysis of high resolution satellite image in the urban area has lots of difficulty including a shadow, the difference of illumination with time, the complexity of image so that the present techniques are seemed to be impossible to resolve. This paper proposes a new way of change detection of building objects in urban area, in which the objects in digital vector map are designated and superimposed on the the high-resolution satellite image. The proposed way makes the buildings on the vector map parameterize, and searches them in the preprocessed high-resolution satellite image by using generalized Hough transform. The designated building objects are overlaid on the satellite image and the result can help to search the changes in building objects rapidly.

• Korean Journal of Construction Engineering and Management
• /
• v.6 no.6 s.28
• /
• pp.90-97
• /
• 2005

Poor usage of work-continuity for planning and management is one of the leading causes of decreased productivity in high-rise and complexity construction projects. For efficient finish work, tact scheduling method needs to be implemented according to tact time. But there are the studies about zoning of work area, daily construction information and tact planning and management, there are not the studies about tact time yet. The purpose of this study is to help implementation of tact scheduling by tact time and adjusted work-plan. The main contents of this study are as follow; (1)Tact time has been calculated as coordination of work-plan between a general contractor and specialties. (2)Project-plan can be without delay by tact time calculation method.

• The KIPS Transactions:PartB
• /
• v.12B no.3 s.99
• /
• pp.265-272
• /
• 2005

In this paper, we propose a technique which is speedily searching for correspondent points of two images using Voronoi-Distance, as an image registration method for feature based image mosaics. It extracts feature points in two images by the SUSAN corner detector, and then create not only the Voronoi Surface which has distance information among the feature points in the base image using a priority based Voronoi distance algorithm but also select the model area which has the maximum variance value of coordinates of the feature points in the model image. We propose a method for searching for the correspondent points in the Voronoi surface of the base image overlapped with the model area by use of the partitive search algorithm using queues. The feature of the method is that we can rapidly search for the correspondent points between adjacent images using the new Voronoi distance algorithm which has $O(width{\times}height{\times}logN)$ time complexity and the the partitive search algerian using queues which reduces the search range by a fourth at a time.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.30 no.4C
• /
• pp.230-238
• /
• 2005

An orthogonal frequency division multiplexing (OFDM) system consists of a number of independently modulated subcarriers and, thus, a high peak-to-average power ratio (PAR) can occur when the subcarriers are added coherently. The high PAR brings such disadvantages as an increased complexity of the analog-to-digital (ADC) and digital-to-analog (DAC) converters and a reduced efficiency of the radio frequency (RF) power amplifier. In this paper, we propose a novel PAR reduction scheme called selective mapping of partial tones (SMOPT). The SMOPT scheme has a reduced complexity, lower sensitivity to peak reduction tones (PRT) positions, and a shorter processing time as compared with the conventional tone reservation (TR) scheme. The performance of the SMOPT scheme is analyzed based on the IEEE 802.1la wireless local area network(WLAM) physical layer model. Numerical results show that the SMOPT scheme outperforms the TR scheme under various scenarios.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.9 no.4
• /
• pp.409-416
• /
• 2014

In H/W implementation for the finite field, the use of normal basis has several advantages, especially the optimal normal basis is the most efficient to H/W implementation in $GF(2^m)$. The finite field $GF(2^m)$ with type I optimal normal basis(ONB) has the disadvantage not applicable to some cryptography since m is even. The finite field $GF(2^m)$ with type II ONB, however, such as $GF(2^{233})$ are applicable to ECDSA recommended by NIST. In this paper, we propose a bit-parallel multiplier over $GF(2^m)$ having a type II ONB, which performs multiplication over $GF(2^m)$ in the extension field $GF(2^{2m})$. The time and area complexity of the proposed multiplier is the same as or partially better than the best known type II ONB bit-parallel multiplier.

• Korean Institute of Interior Design Journal
• /
• v.26 no.5
• /
• pp.135-142
• /
• 2017

Recently, as human-centered design and humanization of space accelerates, the concept of physical space is changing to user-centered space. In particular, in the case of exhibition space to utilize digital media, visitors' actively experiencing exhibits and participating exhibition are regarded as an important factor, thus affordance design serves as a crucial factor to afford satisfaction with exhibition space to the visitors. Accordingly, the study is to understand the concept of the affordance and the digital media exhibition environment and to analyze the preference for each affordance design factor in the digital exhibition environment. The survey is conducted to people in the twenties who inhabit Seoul and the metropolitan area, familiar with the digital media. The results of the survey show that the most important role of the digital media in the exhibition environment is to create the atmosphere for concentration and complexity is the most preferable among interactivity, network ability and complexity, the feature of the digital media. Additionally, the results reveal that cognitive affordance presenting the feature of design to help the user when he/she want to know something is the most preferable among sensory affordance, physical affordance, cognitive affordance and functional affordance and as the time exposed to the digital media increases the importance of the affordance design is high. As the digital environment is common now in many fields, it will be regarded as a crucial factor to the visitors of an exhibit hall from now on whether affordance design is used.

• KIISE Transactions on Computing Practices
• /
• v.23 no.9
• /
• pp.535-541
• /
• 2017

Today, the scale of the computer software market has increased, and massive sized software has been developed to satisfy diverse requirements. In this context, software complexity is increasing and the quality of software is becoming more difficult to manage. In particular, software reuse is important for the improvement of the environments of legacy systems and new system development. In this paper, we propose a method to reuse modules that are certified by quality. Reusable levels are divided into code area (method, class, and component), project domain, and business levels. Based on the coupling and cohesion of software complexity, we propose a reusable module extraction mechanism with reusability metrics, which constructs a visualization of the "reusable module's chunk" based on the method and class levels. By applying reverse engineering to legacy projects, it is possible to identify reusable modules/objects/chunks. If these modules/objects/chunks are to be reused to develop an extension system or similar new system, we need to ensure software reliability in order to reduce the time and cost of software development.

• Journal of Communications and Networks
• /
• v.13 no.5
• /
• pp.481-493
• /
• 2011

Multiple-input multiple-output (MIMO) technology provides high data rate and enhanced quality of service for wireless communications. Since the benefits from MIMO result in a heavy computational load in detectors, the design of low-complexity suboptimum receivers is currently an active area of research. Lattice-reduction-aided detection (LRAD) has been shown to be an effective low-complexity method with near-maximum-likelihood performance. In this paper, we advocate the use of systolic array architectures for MIMO receivers, and in particular we exhibit one of them based on LRAD. The "Lenstra-Lenstra-Lov$\acute{a}$sz (LLL) lattice reduction algorithm" and the ensuing linear detections or successive spatial-interference cancellations can be located in the same array, which is considerably hardware-efficient. Since the conventional form of the LLL algorithm is not immediately suitable for parallel processing, two modified LLL algorithms are considered here for the systolic array. LLL algorithm with full-size reduction-LLL is one of the versions more suitable for parallel processing. Another variant is the all-swap lattice-reduction (ASLR) algorithm for complex-valued lattices, which processes all lattice basis vectors simultaneously within one iteration. Our novel systolic array can operate both algorithms with different external logic controls. In order to simplify the systolic array design, we replace the Lov$\acute{a}$sz condition in the definition of LLL-reduced lattice with the looser Siegel condition. Simulation results show that for LR-aided linear detections, the bit-error-rate performance is still maintained with this relaxation. Comparisons between the two algorithms in terms of bit-error-rate performance, and average field-programmable gate array processing time in the systolic array are made, which shows that ASLR is a better choice for a systolic architecture, especially for systems with a large number of antennas.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.17 no.1
• /
• pp.33-39
• /
• 2007

Finite field multipliers are the basic building blocks in many applications such as error-control coding, cryptography and digital signal processing. Hence, the design of efficient dedicated finite field multiplier architectures can lead to dramatic improvement on the overall system performance. In this paper, a new bit serial structure for a multiplier with low latency in Galois field is presented. To speed up multiplication processing, we divide the product polynomial into several parts and then process them in parallel. The proposed multiplier operates standard basis of $GF(2^m)$ and is faster than bit serial ones but with lower area complexity than bit parallel ones. The most significant feature of the proposed architecture is that a trade-off between hardware complexity and delay time can be achieved.