• Transactions on Electrical and Electronic Materials
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• v.18 no.1
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• pp.55-57
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• 2017

Amorphous oxide thin film transistors (TFTs) were fabricated with 0.5 wt% silicon doped zinc tin oxide (a-0.5SZTO) thin film deposited by radio frequency (RF) magnetron sputtering. In order to investigate the effect of annealing treatment on the electrical properties of TFTs, a-0.5SZTO thin films were annealed at three different temperatures ($300^{\circ}C$, $500^{\circ}C$, and $700^{\circ}C$ for 2 hours in a air atmosphere. The structural and electrical properties of a-0.5SZTO TFTs were measured using X-ray diffraction and a semiconductor analyzer. As annealing temperature increased from $300^{\circ}C$ to $500^{\circ}C$, no peak was observed. This provided crystalline properties indicating that the amorphous phase was observed up to $500^{\circ}C$. The electrical properties of a-0.5SZTO TFTs, such as the field effect mobility (${\mu}_{FE}$) of $24.31cm^2/Vs$, on current ($I_{ON}$) of $2.38{\times}10^{-4}A$, and subthreshold swing (S.S) of 0.59 V/decade improved with the thermal annealing treatment. This improvement was mainly due to the increased carrier concentration and decreased structural defects by rearranged atoms. However, when a-0.5SZTO TFTs were annealed at $700^{\circ}C$, a crystalline peak was observed. As a result, electrical properties degraded. ${\mu}_{FE}$ was $0.06cm^2/Vs$, $I_{ON}$ was $5.27{\times}10^{-7}A$, and S.S was 2.09 V/decade. This degradation of electrical properties was mainly due to increased interfacial and bulk trap densities of forming grain boundaries caused by the annealing treatment.

• Korean Journal of Materials Research
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• v.11 no.10
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• pp.879-888
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• 2001

The effects of final annealing temperature on the microstructure and creep characteristics were investigated for the Zr-lNb-0.2X (X=0, Mo, Cu) and Zr-lNb- 1Sn-0.3Fe-0.1X (X=0, Mo, Cu) alloys. The microstructures were observed by using TEM/EDS, and grain size and distributions of precipitates were analyzed using a image analyzer. The creep test was performed at $400^{\circ}C$ under applied stress of 150 MPa for 10 days. The $\beta$-Zr was observed at annealing temperature above $600^{\circ}C$. In the temperature above$ 600^{\circ}C$, the grain sizes of both alloy systems appeared to be increased with increasing the final annealing temperature. The creep strengths of Zr-1Nb-1Sn-0.3Fe-0.1X alloys were higher than those of Zr-1Nb-0.2X ones due to the effect of solid solution hardening by Sn in Zr-lNb-lSn-0.3Fe-0.1X alloy system. Also, Mo addition showed the strong effect of precipitate hardening in both alloy systems. The creep strength rapidly decreased with increasing the annealing temperature up to $600^{\circ}C$. However, a superior creep resistance was obtained in the sample that annealed to have a second phase of $\beta$-Zr. It was considered that the appearance of $\beta$-Zr would play an important role in the strengthening mechanism of creep deformation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.05a
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• pp.9-14
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• 1996

The dependence of microstructural and optical properties of Ag-In-Sb-Te thin films on annealing heat-treatments was studied. It was found from the present work that the increase of reflectance after annealing heat-treatment is related with phase change of Ag-In-Sb-Te thin film from amorphous state to crystalline phases which involve Sb crystalline phase and AgInTe$_2$ stoichiometric phase. On the other hand, the reflectance is decreased after high temperature annealing (above 450$^{\circ}C$), due to the morphology .mange of film surface. For the purpose of practical application(erasable optical disk), we fabricated quadrilayered Ag-In-Sb-Te alloy disk, and annealed it with continuous laser beam. As result of this laser\ulcorner annealing treatment, we found that the increment of reflectance is 9.3% at 780nm wavelength. It might be considered that Ag-In-Sb-Te alloy optical disk is the big promising candidate for the erasable optical memory medium.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2009.05a
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• pp.167-169
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• 2009

We have carried out quantitative structure and property analysis of the nanoporous structures of low dielectric constant (low-k) carbon-doped silicon oxide (SiCOH) films, which were deposited with plasma enhanced chemical vapor deposition (PECVD) using vinyltrimethylsilane (VTMS), divinyldimethylsilane (DVDMS), and tetravinylsilane (TVS) as precursor and oxygen as an oxidant gas. We found that the SiCOH film using VTMS only showed well defined spherical nanopores within the film after thermal annealing at $450^{\circ}C$ for 4 h. The average pore radius of the generated nanopores within VTMS SiCOH film was 1.21 nm with narrow size distribution of 0.2. It was noted that thermally labile $C_{x}H_{y}$ phase and Si-$CH_3$ was removed to make nanopore within the film by thermal annealing. Consequently, this induced that decrease of average electron density from 387 to $321\;nm^{-3}$ with increasing annealing temperature up to $450^{\circ}C$ and taking a longer annealing time up to 4 h. However, the other SiCOH films showed featureless scattering profiles irrespective of annealing conditions and the decreases of electron density were smaller than VTMS SiCOH film. Because, with more vinyl groups are introduced in original precursor molecule, films contain more organic phase with less volatile characteristic due to the crosslinking of vinyl groups. Collectively, the presenting findings show that the organosilane containing vinyl group was quite effective to deposit SiCOH/$C_{x}H_{y}$ dual phase films, and post annealing has an important role on generation of pores with the SiCOH film.

• Journal of the Korean Electrochemical Society
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• v.14 no.3
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• pp.125-130
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• 2011

We describe that the surface and thickness of nanoporous $WO_3$ fabricated by both light-induced and light-absent anodization are affected by pre-annealing process from $200^{\circ}C$ to $600^{\circ}C$. As a result, the nanoporous $WO_3$ with a thickness of $1.83{\mu}m$ can be achieved by anodization for 6 hours after pre-annealing at $400^{\circ}C$ without illumination of light. Moreover, the thickness of nanoporous $WO_3$ fabricated by pre-annealing is thicker than that of $WO_3$ prepared by non-annealing process. However, the light illumination during anodization leads to convert the crystalline structure obtained by pre-annealing, which interfere the growth of nanoporous $WO_3$. In this paper, we discuss about the growth mechanism of these different nanoporous $WO_3$ films.

• Journal of the Korean Vacuum Society
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• v.6 no.1
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• pp.28-35
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• 1997

Effects of rapid thermal annealing on the characteristics of Cu films deposited from the (hfac)Cu(VTMS) precursor and on the barrier properties of TiN layers were studied. By the post-annealing, the electrical characteristics of Cu/TiN and the microstructures of Cu films were significantly changed. The properties of Cu films were more sensitive to the annealing temperature than the annealing time. Sheet resistance started to increase above $400^{\circ}C$, and the interreaction between Cu and Ti and the oxidation of Cu layer were observed above $600^{\circ}C$. The grain growth of Cu with the (111) preferred orientation was found to be most pronounced at $500^{\circ}C$. It revealed that the optimum annealing conditions for MOCVD-Cu/PVD-TiN structures to enhance the electrical characteristics without degradation of TiN barriers were in the range of $400^{\circ}C$.

• Journal of the Korean Society for Heat Treatment
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• v.21 no.6
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• pp.307-313
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• 2008

The tensile deformation and shape recovery behaviors were studied in Ni-Ti shape memory wires showing different transformation characteristics by annealing at $200{\sim}600^{\circ}C$. Both R phase ${\rightarrow}$ B19' martensitic transformation at lower temperature and B2 ${\rightarrow}$ R phase transformation at higher temperature occurred in the shape memory wires annealed at $200{\sim}500^{\circ}C$. Transformation temperature and heat flow of B19' martensite increase but those of R phase main almost constant even with increasing annealing temperature. In the case of wires annealed and then cooled to $20^{\circ}C$, plateau on stress-strain curves in tensile testing can be observed due to the collapse of R phase variants and the formation of deformation-induced B19' martensite. In the case of wires annealed and then cooled to $-196^{\circ}C$, however, plateau on stress-strain curves does not appear and stress increases steadily with increasing tensile deformation. Comparing shape recovery rate with cooling temperature after annealing, shape recovery rate of the wire cooled to $20^{\circ}C$ is higher than that of the wire cooled to $-196^{\circ}C$ after annealing, and maximum shape recovery rate of 95% appears in the wire annealed at $400^{\circ}C$ and then cooled to $20^{\circ}C$. $R_s$ and $R_f$ temperatures measured during shape recovery tests are higher than $A_s$ and $A_f$ temperatures measured by DSC tests even at the same annealing temperature.

• Journal of the Korean Electrochemical Society
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• v.8 no.1
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• pp.24-31
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• 2005

Ion shower doping with a main ion source of $P_2H_x$ using a source gas mixture of $PH_3/H_2$ was conducted on excimer-laser-annealed (ELA) poly-Si.The crystallinity of the as-implanted samples was measured using a UV-transmittance. The measured value using UV-transmittance was found to correlate well with the one measured using Raman Spectroscopy. The sheet resistance decreases as the acceleration voltage increases from 1kV to 15kV at the moderate doping conditions. It, however, increases as the acceleration voltage increases under the severe doping conditions. The reduction in carrier concentration due to electron trapping at uncured damage after activation annealing seems to be responsible for the rise in sheet resistance. Three different annealing methods were investigated in terms of dopant-activation and damage-recovery, such as furnace annealing, excimer laser annealing, and rapid thermal annealing, respectively.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.8
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• pp.335-341
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• 2003

The composites were fabricated respectively 61vo1.% $\beta$ -SiC and 39vo1.% Ti $B_2$ spray-dried powders with the liquid forming additives of l2wt% $Al_2$ $O_3$＋ $Y_2$ $O_3$ by pressureless annealing at 1$700^{\circ}C$, 175$0^{\circ}C$, 180$0^{\circ}C$ for 4 hours. The result of phase analysis of composites by XRD revealed $\alpha$ -SiC(6H), Ti $B_2$, and YAG(A $l_{5}$ $Y_3$ $O_{12}$ ) crystal phase. The relative density, the Young's modulus and fracture toughness showed respectively the highest value of 92.97%, 92.88Gpa and 4.4Mpaㆍ $m^{\frac{1}{2}}$ for composites by pressureless annealing temperature 1$700^{\circ}C$ at room temperature. The electrical resistivity showed the lowest value of 8.09${\times}$10$^{-3}$ ㆍcm for composite by pressureless annealing temperature 1$700^{\circ}C$ at $25^{\circ}C$. The electrical resistivity of the SiC-Ti $B_2$ composites was all positive temperature cofficient resistance(PTCR) in the temperature ranges from $25^{\circ}C$ to $700^{\circ}C$.

• Transactions on Electrical and Electronic Materials
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• v.11 no.2
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• pp.73-76
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• 2010

The copper indium disulfide ($CuInS_2$) thin film was manufactured using sputtering and thermal evaporation methods, and the annealing with sulfurization process was used in the vacuum chamber to the substrate temperature on the glass substrate, the annealing temperature and the composition ratio, and the characteristics thereof were investigated. The $CuInS_2$ thin film was manufactured by the sulfurization of a soda lime glass (SLG) Cu/In/S stacked [1] elemental layer deposited on a glass substrate by vacuum chamber annealing [2] with sulfurization for various times at a temperature of substrate temperature of $200^{\circ}C$. The structure and electrical properties of the film was measured in order to determine the optimum conditions for the growth of $CuInS_2$ ternary compound semiconductor $CuInS_2$ thin films with a non-stoichiometric composition. The physical properties of the thin film were investigated under various fabrication conditions [3,4], including the substrate temperature, annealing temperature and annealing time by X-ray diffraction (XRD), field Emission scanning electron microscope (FE-SEM), and Hall measurement systems. [5] The sputtering rate depending upon the DC/RF power was controlled so that the composition ratio of Cu versus In might be around 1:1, and the substrate temperature affecting the quality of the film was varied in the range of room temperature (RT) to $300^{\circ}C$ at intervals of $100^{\circ}C$, and the annealing temperature of the thin film was varied RT to $550^{\circ}C$ in intervals of $100^{\circ}C$.