• IEIE Transactions on Smart Processing and Computing
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• v.4 no.3
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• pp.152-157
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• 2015

Various power supply noise sources in a system integrated circuit degrade the performance of a low dropout (LDO) regulator. In this paper, a capacitor-less low dropout regulator for enhanced power supply rejection is proposed to provide good power supply rejection (PSR) performance. The proposed scheme is implemented by an additional capacitor at a gate node of a pass transistor. Simulation results show that the PSR performance of the proposed LDO regulator depends on the capacitance value at the gate node of the pass transistor, that it can be maximized, and that it outperforms a conventional LDO regulator.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.34 no.2
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• pp.145-151
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• 2010

In this study, an absorption power cycle, which can be used for a low-temperature heat source driven power cycle such as geothermal power generation, was investigated and optimized in terms of power by the simulation method. A steady-state simulation model was adopted to analyze and optimize its performance. Simulations were carried out for the given heat source and sink inlet temperatures, and the given flow rates were based on the typical power plant thermal-capacitance-rate ratio. The cycle performance was evaluated for two independent variables: the ammonia fraction at the separator inlet and the maximum cycle pressure. Results showed that the absorption power cycle can generate electricity up to about 14 kW per 1 kg/s of heat source when the heat source temperature, heat sink temperature, and thermal-capacitance-rate ratio are $100^{\circ}C$, $20^{\circ}C$, and 5, respectively.

• Journal of Information Processing Systems
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• v.9 no.1
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• pp.41-52
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• 2013

One of the obstacles preventing the Zigbee protocol from being widely used is the excessive power consumption of Zigbee devices in low bandwidth and low power requirement applications. This paper proposes a protocol that resolves the power efficiency problem. The proposed protocol reduces the power consumption of Zigbee devices in beacon-enabled networks without increasing the time taken by Zigbee peripherals to communicate with their coordinator. The proposed protocol utilizes a beacon control mechanism called a "sleep pattern," which is updated based on the previous event statistics. It determines exactly when Zigbee peripherals wake up or sleep. A simulation of the proposed protocol using realistic parameters and an experiment using commercial products yielded similar results, demonstrating that the protocol may be a solution to reduce the power consumption of Zigbee devices.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.6
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• pp.853-856
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• 2021

In this paper, a low noise amplifier having high gain and low noise by using input and inter stage matching circuits has been designed. A current-reused two-stage common-source topology is adopted, which can obtain high gain and low power consumption. Deterioration of noise characteristics according to the source inductive degeneration matching is compensated by adopting additional matching circuits. Moreover trade-offs among noise, gain, linearity, impedance matching, and power dissipation have been considered. In this design, 0.18-mm CMOS process is employed for the simulation. The simulated results show that the designed low noise amplifier can provide high power gain and low noise characteristics.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.54 no.9
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• pp.434-440
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• 2005

This paper describes an optimized Scheme of reactive-power compensation for the low short-circuit-ratio AC system interconnected with the HVDC system. An HVDC system interconnected with tile low SCR AC system is vulnerable to the ac voltage variation, which brings about the commutation failure of the converter. This problem can be solved using optimized compensation of reactive power. In this study, a benchmark system for HVDC system interconnected with low SCR AC system is derived using PSS/E simulation. Then an optimized srheme for reactive power compensation was derived using integer programming. The feasibility of proposed scheme was analyzed through silnulations with PSS/E and PSCAD/EMTDC. The proposed scheme can compensate the reactive power accurately and minimize the number of switching for harmonic filters and shunt reactors.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.2
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• pp.217-221
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• 2001

In this paper, APLC(Active Power Line Conditioner) is designed for low consumed power electrical equipment such as communication electronic equipment, computer sever and etc.. Because APLC which is hunted to the mains controls only the elements of harmonics, the designed APLC is very high efficient. Additionally, controller designed with low cost micro-controller and analog circuit has good merit economically. Simulation and experimental results on a prototype verify the feasibility of the proposed scheme.

• Journal of Electrical Engineering and Technology
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• v.10 no.1
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• pp.216-226
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• 2015

The neutral beam injection generate ultra-high temperature energy in the tokamak of nuclear fusion. The neutral beam injection make up arc power supply, filament power supply and acceleration & deceleration power supply. The arc power supply has characteristics of low voltage and high current. Arc power supply generate arc through constant output of voltage and current. So this paper proposed suitable buck converter for low voltage and high current. The proposed buck converter used parallel switch because it can be increased capacity and decrease conduction loss. When an arc generated, the neutral beam injection chamber occur high voltage. And it will break output capacitor of buck converter. Therefore the output capacitor was removed in the proposed converter. Thus the proposed converter should be designed for the characteristics of low voltage and high current. Also, the arc power supply should be guaranteed for system stability. The proposed parallel buck converter enables the system stability of the divided low output voltage and high current. The proposed converter with constant output be the most important design of the output inductor. In this paper, designed arc power supply verified operation of system and stability through simulation and prototype. After it is applied to the 288[kW] arc power supply for neutral beam injection.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.149-152
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• 2001

In this paper, a 1.5V 2㎓ low-power peak detector is presented. Analyzing the designed peak detector circuit which is composed with two NMOSs, two diodes, and two capacitors, the detection characteristic relationships are derived. The simulation results with SPICE for 2㎓ pulse signals and sinusoidal signals on the 1.5V supply voltages show the good detection characteristics for input signal levels of 50㎷~500㎷, and show very small power dissipation of 0.332㎽.

• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.3058-3060
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• 2005

In this paper, the CMOS four-quadrant analog multipliers for low-voltage low-power applications are presented. The circuit approach is based on the characteristic of the LV (Low-Voltage) composite transistor which is one of the useful analog building blocks. SPICE simulations are carried out to examine the performances of the designed multipliers. Simulation results are obtained by $0.25{\mu}m$ CMOS parameters with 2V power supply. The LV composite transistor can easily be extended to perform a four-quadrant multiplication. The multiplier has a linear input range up to ${\pm}0.5V$ with a linearity error of less than 1%. The measured -3dB bandwidth is 290MHz and the power dissipation is $37{\mu}W$. The proposed multiplier is expected to be suitable for analog signal processing applications such as portable communication equipment, radio receivers, and hand-held movie cameras.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.425-430
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• 1998

This paper presents a high performance low switching PWM technique for the propulsion system of railway such as subway and high speed train. In order to achieve the continuous voltage control to six-step and a low harmonics with low switching frequency under 500Hz, the synchronous PWM technique is combined with a space vector overmodulation and implemented by using DSP. Improved performance and a validation of proposed method are showed by the digital simulation and the experimental results using a 1.65MVA IGBT VVVF inverter and inertia load equivalent to 160 tons railway vehicles.