• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.6
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• pp.187-194
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• 2005

In this paper, an efficient and fast algerian to reduce calculation amount of FIR(Finite Impulse Responses) filtering is proposed. Proposed algorithm enables arbitrary size of parallel processing, and their structures are also easily derived. Furthermore, it is shown that the number of multiplication/sample is reduced, and number of instructions using MAC(Multiplication and Accumulation) processor are also reduced. For theoretical improvement numbers of sub filters are compared with those of conventional algorithm. In addition to the theoretical improvement, it is shown that number of element for hardwired implementation are reduced comparison to those of the conventional algorithm.

• Journal of IKEEE
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• v.16 no.4
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• pp.310-315
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• 2012

This thesis is intended to design multi thread mobile GPGPU optimized in mobile environment, and to verify an effective thread management method of the multi thread mobile processor. In thread management, there is no management hardware and implement with software instructions. For the verification of the multi thread management method, Lane detection algorithm was implemented to compare nVidia's CUDA Architecture and the designed GPGPU in terms of thread management efficiency. The number of thread is normalized to 48 threads. An implemented Land Detection Algorithm is composed of Gaussian filter algorithm and Sobel Edge Detection algorithm. As a result, the designed GPGPU's thread efficiency is up to 2 times higher than CUDA's thread efficiency.

• KSBB Journal
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• v.22 no.6
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• pp.387-392
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• 2007

Recently, microfluidic biochips for DNA microarray are providing a number of advantages such as, reduction in reagent volume, high-throughput parallel sample screening, automation of processing, and reduction in hybridization time. Particularly, the enhancement of target probe hybridization by decrease of hybridization time is an important aspect highlighting the advantage of microfluidic DNA microarray platform. Fundamental issues to overcome extremely slow diffusion-limited hybridization are based on physical, electrical or fluidic dynamical mixing technology. So far, there have been some reports on the enhancement of the hybridization with the microfluidic platforms. In this review, their principle, performance, and outreaching of the technology are overviewed and discussed for the implementation into many bio-applications.

• Journal of Navigation and Port Research
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• v.26 no.2
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• pp.183-188
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• 2002

The forecast of a container traffic has been very important for port and development. Generally, Statistic methods, such as moving average method, exponential smoothing, and regression analysis have been much used for traffic forecasting. But, considering various factors related to the port affect the forecasting of container volume, neural network of parallel processing system can be effective to forecast container volume based on various factors. This study discusses the forecasting of volume by using the neural, network with back propagation learning algorithm. Affected factors are selected based on impact vector on neural network, and these selected factors are used to forecast container volume. The proposed the forecasting algorithm using neural network was compared to the statistic methods.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.4
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• pp.756-765
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• 2001

An effective dexterous motion control method of redundant robot manipulators based on neural optimization network is proposed to satisfy multi-criteria such as singularity avoidance, minimizing energy consumption, and avoiding physical limits of actuator, while performing a given task. The method employs a neural optimization network with parallel processing capability, where only a simple geometric analysis for resolved motion of each joint is required instead of computing of the Jacobian and its pseudo inverse matrix. For dexterous motion, a joint geometric manipulability measure(JGMM) is proposed. JGMM evaluates a contribution of each joint differential motion in enlarging the length of the shortest axis among principal axes of the manipulability ellipsoid volume approximately obtained by a geometric analysis. Redundant robot manipulators is then controlled by neural optimization networks in such a way that 1) linear combination of the resolved motion by each joint differential motion should be equal to the desired velocity, 2) physical limits of joints are not violated, and 3) weighted sum of the square of each differential joint motion is minimized where weightings are adjusted by JGMM. To show the validity of the proposed method, several numerical examples are illustrated.

• Advances in robotics research
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• v.1 no.1
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• pp.81-99
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• 2014

This paper contributes towards the development of a computer vision system for telemonitoring of industrial articulated robotic arms. The system aims to provide precision real time measurements of the joint angles by employing low cost cameras and visual markers on the body of the robot. To achieve this, a mathematical model that connects image features and joint angles was developed covering rotation of a single joint whose axis is parallel to the visual projection plane. The feature that is examined during image processing is the varying area of given circular target placed on the body of the robot, as registered by the camera during rotation of the arm. In order to distinguish between rotation directions four targets were used placed every $90^{\circ}$ and observed by two cameras at suitable angular distances. The results were deemed acceptable considering camera cost and lighting conditions of the workspace. A computational error analysis explored how deviations from the ideal camera positions affect the measurements and led to appropriate correction. The method is deemed to be extensible to multiple joint motion of a known kinematic chain.

• Journal of the Korea Society for Simulation
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• v.24 no.3
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• pp.17-26
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• 2015

A cluster tool used in many kinds of semiconductor processes for improving the performance and the quality of wafers has a simple configuration, but its schedule is not easy because of its parallel processing module, a lack of intermediate buffers, and time constraints. While there have been many studies on its schedule, most of them have focused on full cycles in which identical work cycles are repeated under constant task times. In this research, we suggest strategies of start-up transient scheduling which satisfies time constraints and converges into a desirable steady schedule for full work cycle. The proposed schedules are expected robust under the stationary stochastic task times. Finally, we show that the strategies make schedules enters the desirable steady schedule and robust using the simulation.

• Journal of Korea Society of Industrial Information Systems
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• v.24 no.1
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• pp.31-38
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• 2019

In this paper, we develop a beamforming front end platform with pipeline circuit configuration method that can apply various clinical diagnostic applications of ultrasound image technology. Hardware design targets compression applications as well as scalable applications where power, integration levels and replication possibilities are important. Firmware design was implemented to achieve optimal FPGA parallel processing level by constructing new IP and system-oriented design environment to accelerate design productivity with maximum productivity improvement using Vivado HLS tool, which is a next generation high level synthesis tool. Former supports the high-speed management function of scan data that can create an image area arbitrarily and can be appropriately corrected and supplemented when reconfiguring or changing system specifications in the future.

• KIPS Transactions on Computer and Communication Systems
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• v.12 no.1
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• pp.41-46
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• 2023

Iterative reconstruction of CT takes a long time because projection and back-projection are alternatively repeated until taking a good image. To reduce the reconstruction time, we need a fast algorithm for calculating the projection which is a time-consuming step. In this paper, we proposed a new algorithm to calculate the line integral and the algorithm is approximately 10% faster than the well-known Siddon method (Jacobs version) and has a good image quality. Although the algorithm has been investigated for the case of parallel beams, it can be extended to the case of fan and cone beam geometries in the future.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.8
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• pp.337-347
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• 2007

An embedded system is called a multi-mode embedded system if it performs multiple applications by dynamically reconfiguring the system functionality. Further, the embedded system is called a multi-mode multi-task embedded system if it additionally supports multiple tasks to be executed in a mode. In this Paper, we address a HW/SW partitioning problem, that is, HW/SW partitioning of multi-mode multi-task embedded applications with timing constraints of tasks. The objective of the optimization problem is to find a minimal total system cost of allocation/mapping of processing resources to functional modules in tasks together with a schedule that satisfies the timing constraints. The key success of solving the problem is closely related to the degree of the amount of utilization of the potential parallelism among the executions of modules. However, due to an inherently excessively large search space of the parallelism, and to make the task of schedulabilty analysis easy, the prior HW/SW partitioning methods have not been able to fully exploit the potential parallel execution of modules. To overcome the limitation, we propose a set of comprehensive HW/SW partitioning techniques which solve the three subproblems of the partitioning problem simultaneously: (1) allocation of processing resources, (2) mapping the processing resources to the modules in tasks, and (3) determining an execution schedule of modules. Specifically, based on a precise measurement on the parallel execution and schedulability of modules, we develop a stepwise refinement partitioning technique for single-mode multi-task applications. The proposed techniques is then extended to solve the HW/SW partitioning problem of multi-mode multi-task applications. From experiments with a set of real-life applications, it is shown that the proposed techniques are able to reduce the implementation cost by 19.0% and 17.0% for single- and multi-mode multi-task applications over that by the conventional method, respectively.