• Journal of the Korea Institute of Military Science and Technology
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• v.13 no.5
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• pp.894-902
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• 2010

This paper presents a vision-based robust off-road terrain classification method against environmental variation. As a supervised classification algorithm, we applied a neural network classifier using wavelet features extracted from wavelet transform of an image. In order to get over an effect of overall image feature variation, we adopted environment sensors and gathered the training parameters database according to environmental conditions. The robust terrain classification algorithm against environmental variation was implemented by choosing an optimal parameter using environmental information. The proposed algorithm was embedded on a processor board under the VxWorks real-time operating system. The processor board is containing four 1GHz 7448 PowerPC CPUs. In order to implement an optimal software architecture on which a distributed parallel processing is possible, we measured and analyzed the data delivery time between the CPUs. And the performance of the present algorithm was verified, comparing classification results using the real off-road images acquired under various environmental conditions in conformity with applied classifiers and features. Experiments show the robustness of the classification results on any environmental condition.

• Journal of Sensor Science and Technology
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• v.27 no.6
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• pp.362-367
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• 2018

A complementary metal oxide semiconductor (CMOS) binary image sensor is proposed for low-power and low-noise operation. The proposed binary image sensor has the advantages of reduced power consumption and fixed pattern noise (FPN). A gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector is used as the proposed CMOS binary image sensor. The GBT PMOSFET-type photodetector has a floating gate that amplifies the photocurrent generated by incident light. Therefore, the sensitivity of the GBT PMOSFET-type photodetector is higher than that of other photodetectors. The proposed CMOS binary image sensor consists of a pixel array with $394(H){\times}250(V)$ pixels, scanners, bias circuits, and column parallel readout circuits for binary image processing. The proposed CMOS binary image sensor was analyzed by simulation. Using the dynamic comparator, a power consumption reduction of approximately 99.7% was achieved, and this performance was verified by the simulation by comparing the results with those of a two-stage comparator. Also, it was confirmed using simulation that the FPN of the proposed CMOS binary image sensor was successfully reduced by use of the double sampling process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.4
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• pp.388-393
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• 2019

As a fiiting method to data with outliers, RANSAC(RANdom SAmple Consensus) based algorithm is widely used in fitting of line, circle, ellipse, etc. CUDA is currently most widely used GPU with massive parallel processing capability. This paper proposes an efficient CUDA implementation of multiple planes fitting using RANSAC with 3d points data, of which one set of 3d points is used for one plane fitting. The performance of the proposed algorithm is demonstrated compared with CPU implementation using both artificially generated data and real 3d heights data of a PCB. The speed-up of the algorithm over CPU seems to be higher in data with lower inlier ratio, more planes to fit, and more points per plane fitting. This method can be easily applied to a wide variety of other fitting applications.

• Nuclear Engineering and Technology
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• v.51 no.1
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• pp.13-30
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• 2019

This paper presents the recent improvements in the DeCART code for HTGR analysis. A new 190-group DeCART cross-section library based on ENDF/B-VII.0 was generated using the KAERI library processing system for HTGR. Two methods for the eigen-mode adjoint flux calculation were implemented. An azimuthal angle discretization method based on the Gaussian quadrature was implemented to reduce the error from the azimuthal angle discretization. A two-level parallelization using MPI and OpenMP was adopted for massive parallel computations. A quadratic depletion solver was implemented to reduce the error involved in the Gd depletion. A module to generate equivalent group constants was implemented for the nodal codes. The capabilities of the DeCART code were improved for geometry handling including an approximate treatment of a cylindrical outer boundary, an explicit border model, the R-G-B checker-board model, and a super-cell model for a hexagonal geometry. The newly improved and implemented functionalities were verified against various numerical benchmarks such as OECD/MHTGR-350 benchmark phase III problems, two-dimensional high temperature gas cooled reactor benchmark problems derived from the MHTGR-350 reference design, and numerical benchmark problems based on the compact nuclear power source experiment by comparing the DeCART solutions with the Monte-Carlo reference solutions obtained using the McCARD code.

• Steel and Composite Structures
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• v.50 no.5
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• pp.583-594
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• 2024

In this paper, a Guided Simulated Annealing (GSA) algorithm is presented to optimize 2D and 3D steel frames against Progressive Collapse. Considering the nature of structural optimization problems, a number of restrictions and improvements have been applied to the decision mechanisms of the algorithm without harming the randomness. With these improvements, the algorithm aims to focus relatively on the flawed variables of the analyzed frame. Besides that, it is intended to be more rational by instituting structural constraints on the sections to be selected as variables. In addition to the LRFD restrictions, the alternate path method with nonlinear dynamic procedure is used to assess the risk of progressive collapse, as specified in the US Department of Defense United Facilities Criteria (UFC) Design of Buildings to Resist Progressive Collapse. The entire optimization procedure was carried out on a C# software that supports parallel processing developed by the authors, and the frames were analyzed in SAP2000 using OAPI. Time history analyses of the removal scenarios are distributed to the processor cores in order to reduce computational time. The GSA produced 3% lighter structure weights than the SA (Simulated Annealing) and 4% lighter structure weights than the GA (Genetic Algorithm) for the 2D steel frame. For the 3D model, the GSA obtained 3% lighter results than the SA. Furthermore, it is clear that the UFC and LRFD requirements differ when the acceptance criteria are examined. It has been observed that the moment capacity of the entire frame is critical when designing according to UFC.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.4
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• pp.384-394
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• 1999

This paper deals with a fixed frequency full-bridge inverter type DC-DC high-power converter with high frequency high voltage(HFHV) transformer-coupled stage, which operates under quasi-resonant ZVS transition priciple in spite of a wide PWM-based voltage regulation processing and largely-changed load conditions. This multi-resonant(MR) converter topology is composed of a series capacitor-connected parallel resonant tank which makes the most of parasitic circuit reactive components of HFHV transformer and two additional quasi-resonant pole circuits incorporated into the bridge legs. The soft-switching operation and practical efficacy of this new converter circuit using the latest IGBTs are actually ascertained through 50kV trially-produced converter system operating using 20kHz/30kHz high voltage(HV) transformers which is applied for driving the diagnostic HV X-ray tube load in medical equipments. It is proved from a practical point of view that the switching losses of IGBTs and their electrical dynamic stresses relating to EMI noise can be considerably reduced under a high frequency(HF) switching-based phase-shift PWM control process for a load setting requirements.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.6
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• pp.23-33
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• 1996

The exploitation of locality of reference in shared memory NUMA multiprocessors is one of the improtant problems in parallel processing today. In this paper, we propose a revised hardeare reference counter to help operating system to manage locality. In contrast to the previous one, the value of counter can abe adjusted dynamically and periodically to adapt the page replication policy to the various memory reference patterns of processors. We use execution-driven simulation of real applications to evaluate the effectiveness of our adjustable DELAY counter. Our main conclusijon is that by using the adjustable DELAY counter the t normalized average memory access costs and the variance of them become smaller for most applications than the previous one and more robust memory management policies can be provided for the operating systems.

• IEMEK Journal of Embedded Systems and Applications
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• v.9 no.6
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• pp.335-344
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• 2014

As a kind of 2D spatial coordinate transform, image warping is a basic image processing technique utilized in various applications. Though image warping algorithm is composed of relatively simple operations such as memory accesses and computations of weighted average, real-time implementations on embedded vision systems suffer from limited computational power because the simple operations are iterated as many times as the number of pixels. This paper presents a real-time implementation of a look-up table(LUT)-based image warping using an FPGA. In order to ensure sufficient data transfer rate from memories storing mapping LUT and image data, appropriate memory devices are selected by analyzing memory access patterns in an LUT-based image warping using backward mapping. In addition, hardware structure of a parallel and pipelined architecture is proposed for fast computation of bilinear interpolation using fixed-point operations. Accuracy of the implemented hardware is verified using a synthesized test image, and an application to real-time lens distortion correction is exemplified.

• Journal of KIISE:Software and Applications
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• v.31 no.11
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• pp.1534-1542
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• 2004

A novel vision-based scheme of extracting real-time traffic information parameters is presented. The method is based on a region classification followed by a spatio-temporal image analysis. The detection region images for each traffic lane are classified into one of the three categories: the road, the vehicle, and the shadow, using statistical and structural features. Misclassification in a frame is corrected by using temporally correlated features of vehicles in the spatio-temporal image. Since only local images of detection regions are processed, the real-time operation of more than 30 frames per second is realized without using dedicated parallel processors, while ensuring detection performance robust to the variation of weather conditions, shadows, and traffic load.

• Journal of Computational Design and Engineering
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• v.2 no.1
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• pp.55-66
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• 2015

To satisfy safety regulations of Economic Commission for Europe (ECE), the surface regions of automobile parts must have a sufficient degree of roundness if there is any chance that they could contact a sphere of 50.0 mm radius (exterior parts) or 82.5 mm radius (interior parts). In this paper, a new offset-based method is developed to automatically detect the possible sphere-contacting shape of such parts. A polyhedral model that precisely approximates the part shape is given as input, and the offset shape of the model is obtained as the Boolean union of the expanded shapes of all surface triangles. We adopt a triple-dexel representation of the 3D model to enable stable and precise Boolean union computations. To accelerate the dexel operations in these Boolean computations, a new parallel processing method with a pseudo-list structure and axis-aligned bounding box is developed. The possible sphere-contacting shape of the part surface is then extracted from the offset shape as a set of points or a set of polygons.