• The KIPS Transactions:PartA
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• v.15A no.6
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• pp.345-350
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• 2008

Recently, a HyperStar network HS(2n,n) has been introduced as a new interconnection network of new topology for parallel processing. HyperStar network has properties of hypercube and star graph, further improve the network cost of a hypercube with the same number of nodes. In this paper, we show a construction algorithm of edge-disjoint spanning trees in HyperStar network HS(2n,n). Also, we prove that edge-disjoint spanning tree by the algorithm is optimal.

• Annual Conference of KIPS
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• 2021.11a
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• pp.201-204
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• 2021

PIPO 경량 블록암호는 ICISC'20에서 발표된 암호이다. 본 논문에서는 PIPO의 단일 평문 최적화 구현과 4평문 병렬 구현을 제안한다. 단일 평문 최적화 구현은 Rlayer의 최적화와 키스케쥴을 포함하지 않은 구현을 진행하였다. 결과적으로 키스케쥴을 포함하는 기존 연구 대비 70%의 성능 향상을 확인하였다. 4평문의 경우 32-bit 레지스터를 최대한 활용하여, 레지스터 내부 정렬과 Rlayer의 최적화 구현을 진행하였다. 또한 Addroundkey 구현에서 메모리 최적화 구현과 속도 최적화 구현을 나누어 구현하였다. 메모리 사용을 줄인 메모리 최적화 구현은 단일 평문 구현 대비 80%의 성능 향상을 확인하였고, 암호화 속도를 빠르게 구현한 속도 최적화 구현은 단일 평문 구현 대비 157%의 성능 향상을 확인하였다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.1
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• pp.340-367
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• 2018

Storage services integration can be done for achieving high availability, improving data access performance and scalability while preventing vendor lock-in. However, multiple services environment management and interoperability have become a critical issue as a result of service architectures and communication interfaces heterogeneity. Storage federation model provides the integration of multiple heterogeneous and self-sufficient storage systems with a single control point and automated decision making about data distribution. In order to integrate diverse heterogeneous storage services into a single storage pool, we are proposing a storage service federation framework named BoxBroker. Moreover, an automated decision model based on a policy-driven data distribution algorithm and a service evaluation method is proposed enabling BoxBroker to make optimal decisions. Finally, a demonstration of our proposal capabilities is presented and discussed.

• 한국전산유체공학회:학술대회논문집
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• 2005.04a
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• pp.41-46
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• 2005

A new PC cluster was designed and constructed based on Windows XP Operating system. Primary target of the present design was the high node density per rack by using the general PC parts those are cost-effective and readily available in the market. Other major design points were system cooling and the convenient maintenance using standard PC parts. Presently 24 nodes per rack seems to be optimum considering the specification of the network switching device, system cooling and power supply, but 40 nodes can be accommodated within a single rack at maximum. Windows XP was selected as a high-performance computing environment considering the cost and the convenience in acquisition, maintenance and education. Both fast-Ethernet and Gigabit Ethernet network connection were tested and compared with previous data, especially for Linux doter using Myrinet. The result shows that there is no significant difference between the operating systems and the Fast-Ethernet and/or Gigabit Ethernet are good solution for the high-performance PC cluster considering the cost and performance.

• Smart Structures and Systems
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• v.21 no.2
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• pp.151-161
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• 2018

A new type of cascade sandwiched piezoelectric ultrasonic transducer is presented and studied. The cascade transducer is composed of two traditional longitudinally sandwiched piezoelectric transducers, which are connected together in series mechanically and in parallel electrically. Based on the analytical method, the electromechanical equivalent circuit of the cascade transducer is derived and the resonance/anti-resonance frequency equations are obtained. The impedance characteristics and the vibrational modes of the transducer are analyzed. By means of numerical method, the dependency of the resonance/anti-resonance frequency and the effective electromechanical coupling coefficient on the geometrical dimensions of the cascade transducer are studied and some interesting conclusions are obtained. Two prototypes of the cascade transducers are designed and made; the resonance/anti-resonance frequency is measured. It is shown that the analytical resonance/anti-resonance frequencies are in good agreement with the experimental results. It is expected that this kind of cascade transducer can be used in large power and high intensity ultrasonic applications, such as ultrasonic liquid processing, ultrasonic metal machining and ultrasonic welding and soldering.

• 제어로봇시스템학회:학술대회논문집
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• 1998.10a
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• pp.226-231
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• 1998

This paper describes how a priori road geometry and its estimation may be used to detect road boundaries and lane markings in road scene images. We assume flat road and road boundaries and lane markings are all Bertrand curves which have common principal normal vectors. An active contour is used for the detection of road boundary, and we reconstruct its geometric property and make use of it to detect lane markings. Our approach to detect road boundary is based on minimizing energy function including edge related term and geometric constraint term. Lane position is estimated by pixel intensity statistics along the parallel curve shifted properly from boundary of the road. We will show the validity of our algorithm by processing real road images.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.3
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• pp.215-222
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• 2022

Artificial neuromorphic devices are considered the key component in realizing energy-efficient and brain-inspired computing systems. For the artificial neuromorphic devices, various material candidates and device architectures have been reported, including two-dimensional materials, metal-oxide semiconductors, organic semiconductors, and halide perovskite materials. In addition to conventional electrical neuromorphic devices, optoelectronic neuromorphic devices, which operate under a light stimulus, have received significant interest due to their potential advantages such as low power consumption, parallel processing, and high bandwidth. This article reviews the recent progress in optoelectronic neuromorphic devices using various active materials such as two-dimensional materials, metal-oxide semiconductors, organic semiconductors, and halide perovskites

• Journal of Korea Society of Digital Industry and Information Management
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• v.18 no.1
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• pp.1-9
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• 2022

Galois field arithmetic is important in error correcting codes and public-key cryptography schemes. Hardware realization of these schemes requires an efficient implementation of Galois field arithmetic operations. Multiplication is the main finite field operation and designing efficient multiplier can clearly affect the performance of compute-intensive applications. Diverse algorithms and hardware architectures are presented in the literature for hardware realization of Galois field multiplication to acquire a reduction in time and area. This paper presents a low complexity semi-systolic multiplier to facilitate parallel processing by partitioning Montgomery modular multiplication (MMM) into two independent and identical units and two-level systolic computation scheme. Analytical results indicate that the proposed multiplier achieves lower area-time (AT) complexity compared to related multipliers. Moreover, the proposed method has regularity, concurrency, and modularity, and thus is well suited for VLSI implementation. It can be applied as a core circuit for multiplication and division/exponentiation.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.169-172
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• 2000

This paper describes design of cryptographic processor which can execute SEED, DES, and triple DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has I unrolled loop structure with hardware sharing and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation, the precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O technique is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is designed using 2.5V 0.25 $\mu\textrm{m}$ CMOS technology and consists of about 34.8K gates. Its peak performances is about 250 Mbps under 100 Mhz ECB SEED mode and 125 Mbps under 100 Mhz triple DES mode.

• Economic and Environmental Geology
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• v.33 no.1
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• pp.41-50
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• 2000

Geo-radar survey which has the advantage of high-resolution and relatively fast survey has been widely used for engineering and environmental problems. Three-dimensional effects have to be considered in the interpretation of geo-radar for high-resolution. However, there exists a trouble on the analysis of the three dimensional effects. To solve this problem an efficient three dimension numerical modeling algorithm is needed. Numerical radar modeling in three dimensional case requires large memory and long calculating time. In this paper, a finite difference method time domain solution to Maxwell's equations for simulating electromagnetic wave propagation in three dimensional media was developed to make economic algorithm which requires smaller memory and shorter calculating time. And in using boundary condition Liao absorption boundary. The numerical result of cross-hole radar survey for tunnel is compared with real data. The two results are well matched. To prove application to three dimensional analysis, the results with variation of tunnel's incident angle to survey cross-section and the result when the tunnel is parallel to the cross-section were examined. This algorithm is useful in various geo-radar survey and can give basic data to develop dat processing and inversion program.