• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.301-304
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• 2001

The analog multiplier is very useful building block in many circuits such as filter, frequency-shifter, and modulators. In recent year, The main design issue of circuit designer is low-voltage/low-power system design, because of all systems are recommended very integrated system and portable system In this paper, the proposed the four-quadrant analog multiplier is using the bulk-driven techniques. The bulk-driven technique is very useful technique in low-voltage system, compare with gate-driven technique. therefore the proposed analog multiplier is operated in 1V supply voltage. And the proposed analog multiplier is low power dissipation compare with the others. therefor the proposed analog multiplier is convenient in low-voltage/low-power in system.

• 한국초전도학회:학술대회논문집
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• v.9
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• pp.238-241
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• 1999

Analog-to-digital converter has attracted a lot of interests as one of the most prospective area of an application of Josephson Junction technology. Recently, the development of a digital-to-analog converter has been pursued to achieved the high performance. One of the main advantage in using single flux quantum logic in a digital-to-analog converter is the low voltage drop in a single Josephson Junction and hence the resolution of the output voltage of this digital-to-analog converter can be very high. In this work, we have used a software, called WRspice, to study a voltage multiplier circuit which is the basic block in building a digital-to-analog circuit. In simulation, we operated a voltage multiplier with .4 Josephson Junctions per stage and studied the dependence on the circuit bias currents and the circuit inductors of the voltage multiplier. Our simulation results showed a fast operation and reasonable circuit margins.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.244-247
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• 1999

In this paper, a low voltage CMOS analog four-quadrant multiplier is presented. The proposed multiplier is composed of a pair of transconductor and lowers supply voltage down to $V_{T}$+2 $V_{Ds,sat}$+ $V_{DS,triode}$. The designed analog four-quadrant multiplier have simulated by HSPICE using 0.25${\mu}{\textrm}{m}$ n-well CMOS process with a 1.2V supply voltage. Simulation results show that the THD can be 1.28% at maximum differential input of 0.7 $V_{p-p}$././.

• The Journal of the Acoustical Society of Korea
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• v.18 no.3E
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• pp.44-48
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• 1999

The CMOS four-quadrant analog multiplier for low-voltage low-power applications are presented in this thesis. The circuit approach is based on the characteristic of the LV (Low-Voltage) composite transistor which is one of the useful analog building block. SPICE simulations are carried out to examine the performances of the designed multiplier. Simulation results are obtained by 0.6㎛ CMOS parameters with 2V power supply. The basic configuration of the multiplier is the CMOS Gilbert cell with two LV composite transistors. The linear input range of the multiplier is over ±0.4V with a linearity error of less than 1.3%. The measured -3dB bandwidth is 288MHz and the power dissipation is 255 ㎼.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.868-871
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• 2005

In this article, presents an analog multiplier using a general-purpose operational amplifier (opamp). The realization method is based on the quarter-square technique, which utilize the square-law characteristic of the class AB output stage of the opamp. The experimental results verifying the proposed multiplier performances are also included. The linearity error and the total harmonic distortion is about 0.8% and 1.6%, respectively.

• The Journal of the Acoustical Society of Korea
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• v.19 no.1
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• pp.84-88
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• 2000

In this paper, a low voltage CMOS analog four-quadrant multiplier is presented. The proposed multiplier is composed of two fully differential transconductors and lowers supply voltage down to VT+2VDS,sat+VDS,triode. The designed analog four-quadrant multiplier has simulated by HSPICE using 0.25㎛ n-well CMOS process with a 1.2V supply voltage. Simulation results show that the THD can be 1.28% at maximum differential input of 0.7VP-P.

• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.3058-3060
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• 2005

In this paper, the CMOS four-quadrant analog multipliers for low-voltage low-power applications are presented. The circuit approach is based on the characteristic of the LV (Low-Voltage) composite transistor which is one of the useful analog building blocks. SPICE simulations are carried out to examine the performances of the designed multipliers. Simulation results are obtained by $0.25{\mu}m$ CMOS parameters with 2V power supply. The LV composite transistor can easily be extended to perform a four-quadrant multiplication. The multiplier has a linear input range up to ${\pm}0.5V$ with a linearity error of less than 1%. The measured -3dB bandwidth is 290MHz and the power dissipation is $37{\mu}W$. The proposed multiplier is expected to be suitable for analog signal processing applications such as portable communication equipment, radio receivers, and hand-held movie cameras.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.3
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• pp.137-144
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• 1989

A building block approach to generate an analog multiplier architecture is described. Several non-idealities including the effects of the mobility degradation present in a typical operational transconductance amplifier (OTA) are minimized by using a two cross coupled OTA structure. It is shown that the third-order harmonic distortion is cancelled even at high temperatures. It is proved that OTA based approach is suitable for analog singal processing at relatively high temperatures.

• 전기의세계
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• v.14 no.2
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• pp.14-24
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• 1965

The characteristics of servo-multipliers and its accuracies are analyzed. From the analysis a low cost high accuracy four quadrant servo-multiplier with first derivative output feedback is built. The multiplier servomechanism has a second order system response with a damping ratio of 0.8 and computing bandwidth of 4 cycles per second, and its tracking accuracy at low speed of 0.5 volt per second is 0.9 per cent of maximum output voltage and static accuracy is better than 0.6 per cent. Method of testing this multiplier and the results are also described. The test on the characteristics of the multiplier shows that the results agree with theoretical values satisfactorily, and justifies the use of the servo-multiplier for slow type analog computers.

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.80.1-80
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• 2002

In this article, an alternative analog multiplier circuit, using the translinear second-generation current conveyors with the external resistors. The realization method makes use of the inherited translinear loop of the current conveyor offering the positive-supply current that provides in the quartersquare algebraic identity. The proposed circuit operates in voltage mode and it achieves a high accuracy. The PSPICE simulation results confirm that the performances of the proposed multiplier circuit, such as dynamic range and accuracy, are agreed with the theoretical results.