• 전자공학회논문지C
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• 제36C권11호
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• pp.10-17
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• 1999

본 논문에서는 MOS 트랜지스터로만 이루어진 CMOS IADC(Current-mode Analog-to-Digital Converter)를 설계하였다. 각 단은 CSH(Current Sample-and-Hold)와 CCMP(Current Comparator)로 구성된 1.5-비트 비트 셀로 구성되었다. 비트 셀 전단은 CFT(Clock Feedthrough)가 제거된 9-비트 해상도의 차동 CSH를 배치하였고, 각 단 비트 셀의 ADSC(Analog-to-Digital Subconverter)는 2개의 래치 CCMP로 구성되었다. 제안된 IADC를 현대 0.65 ㎛ CMOS 파라미터로 ACAD 시뮬레이션 한 결과, 20 Ms/s에서 100 ㎑의 입력 신호에 대한 SINAD(Signal to Noise-Plus-Distortion)은 47 ㏈ SNR (Signal-to-Noise)는 50 ㏈(8-bit)을 얻었고 35.7 ㎽ 소비전력 특성을 나타냈다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.1001-1002
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• 2006

As most of the powerline modems use spread spectrum modulation method which has strong immunity against the narrowband fading, or psk modulation method, the amplitude of the signal contains no useful informations. In this paper, we used class D amplifier to implement the drive circuit of the analog front end, and showed that it has great superiority over other existing drive circuits in rapidly impedance changing power line channel.

• Journal of electromagnetic engineering and science
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• 제17권3호
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• pp.138-146
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• 2017

A phase-locked dielectric resonator oscillator (PLDRO) is an essential component of millimeter-wave communication, in which phase noise is critical for satisfactory performance. The general structure of a PLDRO typically includes a dual loop of digital phase-locked loop (PLL) and analog PLL. A dual-loop PLDRO structure is generally used. The digital PLL generates an internal voltage controlled crystal oscillator (VCXO) frequency locked to an external reference frequency, and the analog PLL loop generates a DRO frequency locked to an internal VCXO frequency. A dual loop is used to ease the phase-locked frequency by using an internal VCXO. However, some of the output frequencies in each PLL structure worsen the phase noise because of the N divider ratio increase in the digital phase-locked loop integrated circuit. This study examines the design aspects of an interconnected PLL structure. In the proposed structure, the voltage tuning; which uses a varactor diode for the phase tracking of VCXO to match with the external reference) port of the VCXO in the digital PLL is controlled by one output port of the frequency divider in the analog PLL. We compare the proposed scheme with a typical PLDRO in terms of phase noise to show that the proposed structure has no performance degradation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1991년도 추계학술대회 논문집 학회본부
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• pp.189-192
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• 1991

This paper presents a modular structure design of analog Hopfield neural network. Each multiplier consists of four MOS transistors which are connected to an op-amp at the front end of a neuron. A pair of MOS transistor is used in order to maintain linear operation of the synapse and can produce positive or negative synaptic weight. This architecture can be expandable to any size neural network by forming tree structure. By altering the connections, other nework paradigms can also be implemented using this basic modules. The stength of this approach is the expandability and the general applicability. The layout design of a four-neuron fully connected feedback neural network is presented and is simulated using SPICE. The network shows correct retrival of distorted patterns.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
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• pp.166-168
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• 2006

An analog front-end circuit for 13.56MHz ISO/IECl4443 type B compatible RFID tags was designed. The designed circuit includes a rectifier and regulator to generate a stable DC voltage from the RF signal, an over-voltage limiter to protect the circuit from high voltages, an ASK demodulator to extract the data transferred from reader to tag, and a load modulator to transfer data from tag to reader. The functionality of the designed circuit has been verified through simulations using 0.25um CMOS process parameters.

• 반도체디스플레이기술학회지
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• 제14권2호
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• pp.67-72
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• 2015

For the development of UFS device test system, M-PHY specifications should be matched with MIPI-standard which is analog signal protocol. In this paper, the implementation methodology and hardware structure for the M-PHY AFE (Analog Front End) Block was suggested that it can be implemented using universal components without ASIC process. The testing procedure has a jitter problem so to solve the problems we using ASIC process, normally but the ASIC process needs a lot of developing cost making the UFS device test system. In is paper, the suggestion was verified by the output signal which was compared to the MIPI-standard on the Prototype-board using universal components. The board was reduced the jitter on the condition of HS-TX and 5.824 Gbps Mode in SerDes (Serialize-deserializer). Finally, the suggestion and developed AFE block have a useful better than ASIC process on developing costs of the industrial UFS device test system.

• 전자공학회논문지C
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• 제34C권6호
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• pp.37-43
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• 1997

In this paper, an analog-domain powr-reduction technique for a low-voltage CMOS operational amplifier and its application to clock-based VLSI systems are proposed. The proposed technique cuts off the bias current of the op amp during a half cycle of the clock in the sleeping mode and resumes the curent supply sequentially during the remaining cycle of the clock in the normal operating mode. The proposed sequential sbiasing technique reduces about 50% of the op amp power and improves the circuit performance through high phase margin and stable settling behavior of the output voltage. The power-reduction technique is applied to a sample-and-hold amplifier which is one of the critical circuit blocks used in the front-end stage of analog and/or digital integrated systems. The SHA was simulated and analyzed in a 0.8.mu.m n-well double-poly double-metal CMOS technology.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.769-772
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• 2005

This paper describes a low-voltage and low-power channel selection analog front end with continuous-time low pass filters and highly linear programmable-gain amplifier(PGA). The filters were realized as balanced Gm-C biquadratic filters to achieve a low current consumption. High linearity and a constant wide bandwidth are achieved by using a new transconductance(Gm) cell. The PGA has a voltage gain varying from 0 to 65dB, while maintaining a constant bandwidth. A filter tuning circuit that requires an accurate time base but no external components is presented. With a 1-Vrms differential input and output, the filter achieves -85dB THD and a 78dB signal-to-noise ratio. Both the filter and PGA were implemented in a 0.18um 1P6M n-well CMOS process. They consume 3.2mW from a 1.8V power supply and occupy an area of $0.19mm^2$.

• 한국전자파학회논문지
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• 제18권4호
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• pp.379-388
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• 2007

본 논문에서는 사람의 생체 신호를 감지하기 위해 1.6 GHz 단일 채널 도플러 센서와 아날로그 및 디지털 신호 처리부로 구성되어 있는 실시간 호흡 및 심장 박동 감지기를 개발하였다. 도플러 센서의 RF Front End는 발진기, 믹서, 저잡음 증폭기, 브랜치-라인 하이브리드, 그리고 패치 안테나로 구성되어 있다. 센서에 사용된 브랜치-라인 하이브리드는 기존의 하이브리드에 비해 40 % 정도 크기를 줄이면서도 상당히 유사한 성능을 가지도록 인공 전송 선로(artificial transmission line)를 사용하였다. 아날로그 신호처리부는 2차 Sallen-Key 능동 필터를 사용하여 제작되었고 디지털 신호 처리부는 LabVIEW를 사용하여 컴퓨터상에서 구현되었다. 개발된 시스템은 최대 50 cm 거리에서 사람의 호흡과 심장 박동을 측정함으로써 성능을 검증하였다.

• ETRI Journal
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• 제36권3호
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• pp.352-360
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• 2014

This paper presents a 900 MHz zero-IF RF transceiver for IEEE 802.15.4g Smart Utility Networks OFDM systems. The proposed RF transceiver comprises an RF front end, a Tx baseband analog circuit, an Rx baseband analog circuit, and a ${\Delta}{\Sigma}$ fractional-N frequency synthesizer. In the RF front end, re-use of a matching network reduces the chip size of the RF transceiver. Since a T/Rx switch is implemented only at the input of the low noise amplifier, the driver amplifier can deliver its output power to an antenna without any signal loss; thus, leading to a low dc power consumption. The proposed current-driven passive mixer in Rx and voltage-mode passive mixer in Tx can mitigate the IQ crosstalk problem, while maintaining 50% duty-cycle in local oscillator clocks. The overall Rx-baseband circuits can provide a voltage gain of 70 dB with a 1 dB gain control step. The proposed RF transceiver is implemented in a $0.18{\mu}$ CMOS technology and consumes 37 mA in Tx mode and 38 mA in Rx mode from a 1.8 V supply voltage. The fabricated chip shows a Tx average power of -2 dBm, a sensitivity level of -103 dBm at 100 Kbps with PER < 1%, an Rx input $P_{1dB}$ of -11 dBm, and an Rx input IP3 of -2.3 dBm.