• Journal of Information Display
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• v.7 no.1
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• pp.35-40
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• 2006

Organic light-emitting diode (OLED) display panel using the charge-pump (CP) pixel addressing scheme was fabricated, and the results show that it is applicable for information display. A CP-OLED panel with 64 ${\times}$ 64 pixels consisting of thin-film capacitors and amorphous silicon Schottky diodes was fabricated using conventional thin-film processes. The pixel drive circuit passes electrical current into the OLED cell during most of the frame period as in the thin-film transistor (TFT)-based active-matrix (AM) OLED displays. In this study, the panel was operated at a voltage level of below 4 V, and this operation voltage can be reduced by eliminating the overlap capacitance between the column bus line and the common electrode.

• Journal of Information Display
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• v.13 no.1
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• pp.51-54
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• 2012

In this study, the bias-temperature stress and current-temperature stress induced by the electrical stabilities of half-Corbino hydrogenated-amorphous-silicon (a-Si:H) thin-film transistors (TFTs) with different gate electrode geometries fabricated on the same substrate were examined. The influence of the gate pattern on the threshold voltage shift of the half-Corbino a-Si:H TFTs is discussed in this paper. The results indicate that the half-Corbino a-Si:H TFT with a patterned gate electrode has enhanced power efficiency and improved aperture ratio when compared with the half-Corbino a-Si:H TFT with an unpatterned gate electrode and the same source/drain electrode geometry.

• Journal of the Semiconductor & Display Technology
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• v.19 no.2
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• pp.72-76
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• 2020

The author demonstrated organic ferroelectric thin-film transistors with ferroelectric materials of P(VDF-TrFE) and an amorphous oxide semiconducting In-Ga-Zn-O channel on the silicon substrates. The organic ferroelectric layers were deposited on an oxide semiconductor layer by Langmuir-Blodgett method and then annealed at 128℃ for 30min. The carrier mobility and current on/off ratio of the memory transistors showed 9 ㎠V^-1s^-1 and 6 orders of magnitude, respectively. We can conclude from the obtained results that proposed memory transistors were quite suitable to realize flexible and werable electronic applications.

• Transactions on Electrical and Electronic Materials
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• v.16 no.2
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• pp.99-102
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• 2015

Thin film transistors (TFTs) with amorphous 2 wt% silicon-doped zinc tin oxide (a-2SZTO) channel layer were fabricated using an RF magnetron sputtering system, and the effect of post-annealing treatment time on the structural and electrical properties of a-2SZTO systems was investigated. It is well known that Si can effectively reduce the generation of oxygen vacancies. However, it is interesting to note that prolonged annealing could have a bad effect on the roughness of a-2SZTO systems, since the roughness of a-2SZTO thin films increases in proportion to the thermal annealing treatment time. Thermal annealing can control the electrical characteristics of amorphous oxide semiconductor (AOS) TFTs. It was observed herein that prolonged annealing treatment can cause bumpy roughness, which led to increase of the contact resistance between the electrode and channel. Thus, it was confirmed that deterioration of the electrical characteristics could occur due to prolonged annealing. The longer annealing time also decreased the field effect mobility. The a-2SZTO TFTs annealed at 500℃ for 2 hours displayed the mobility of 2.17 cm²/Vs. As the electrical characteristics of a-2SZTO annealed at a fixed temperature for long periods were deteriorated, careful optimization of the annealing conditions for a-2SZTO, in terms of time, should be carried out to achieve better performance.

• Transactions on Electrical and Electronic Materials
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• v.18 no.3
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• pp.141-143
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• 2017

Novel structured thin film transistors (TFTs) of amorphous silicon zinc tin oxide (a-SZTO) were designed and fabricated with a thin metal layer between the source and drain electrodes. A SZTO channel was annealed at $500^{\circ}C$. A Ti/Au electrode was used on the SZTO channel. Metals are deposited between the source and drain in this novel structured TFTs. The mobility of the was improved from $14.77cm^2/Vs$ to $35.59cm^2/Vs$ simply by adopting the novel structure without changing any other processing parameters, such as annealing condition, sputtering power or processing pressure. In addition, stability was improved under the positive bias thermal stress and negative bias thermal stress applied to the novel structured TFTs. Finally, this novel structured TFT was observed to be less affected by back-channel effect.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.6
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• pp.462-465
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• 2009

Schottky barrier thin film transistors (SB-TFT) on polycrystalline silicon(poly-Si) are fabricated by platinum silicided source/drain for p-type SB-TFT. High quality poly-Si film were obtained by crystallizing the amorphous Si film with excimer laser annealing (ELA) or solid phase crystallization (SPC) method, The fabricated poly-Si SB-TFTs showed low leakage current level and a large on/off current ratio larger than 10), Significant improvement of electrical characteristics were obtained by the additional forming gas annealing in 2% $H_2/N_2$ ambient, which is attributed to the termination of dangling bond at the poly-Si grain boundaries as well as the reduction of interface trap states at gate oxide/poly-Si channel.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.8 no.5
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• pp.49-55
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• 1994

평판 디스플레이용 비정질 실리콘 박막 트랜지스터의 전기적인 특성과 수학적인 모델에 대하여 연구되었고 이론적인 모델은 실험을 통하여 그 타당성을 입증하였다. 게이트전압이 고정된 상태에서 드레인 전압 증가에 따른 드레인 포화전류는 증가되었고 디바이스의 포화는 드레인 전압이 증가될수록 더 증가되었으며 문턱전압은 감소되었다. 세 개의 변수로 구성된 디바이스의 전달특성과 출력특성에 대한 실험 결과값에 대한 모델식이 제시되었는데 이 모델은 디비이스의 기하학적인 구조를 간단화 하기위한 모델식이다.

• Electrical & Electronic Materials
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• v.6 no.2
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• pp.147-151
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• 1993

PECVD에 의해 Burried gate 비정질 실리콘 박막트랜지스터를 제작하여 포화 전압 대 전류 특성에 대하여 새로운 해석을 하였고 해석 결과는 실험적으로 증명되었다. 본 연구의 결과 실험된 전달특성과 출력특성을 모델화 하였는데 이 모델식은 I$_{D}$와 V$_{G}$의 실험결과에서 얻어지는 3가지 함수를 기본으로 모델화 되었다. 포화 드레인 전류는 V$_{G}$가 증가할수록 증가되었고 디바이스의 포화는 드레인 전압이 커질수록 증가되었으며 문턱전압은 감소됨을 보였다.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.20-23
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• 2008

We proposed a-Si:H TFT (hydrogenated amorphous silicon thin film transistor) level shifter which reduced number of power sources. To reduce the number of power sources from four to two, modified bootstrapped inverter was used for the level shifter. The shift register was verified by PSPICE circuit simulation and fabricated. The fabricated level shifter successfully shifted low input (0 to 5 V) to high level output (-7 to 23 V).

• Proceedings of the KIEE Conference
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• 1997.07d
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• pp.1349-1351
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• 1997

TFT2DS was utilized to provide the usefulness as an analytic and design tool. In this paper, the general effects of channel length of an inverted staggered amorphous silicon thin film transistor on its characteristics were investigated. The results obtained from these experiments would be adopted to the optimized device designs and advanced simulations of their electrical properties.