• Korean Journal of Materials Research
• /
• v.18 no.10
• /
• pp.552-556
• /
• 2008

Modified thermal annealing was applied to the activation of the polycrystalline silicon films doped as p-type through implantation of $B_2H_6$. The statistical design of experiments was successfully employed to investigate the effect of rapid thermal annealing on activation of polycrystalline Si doped as p-type. In this design, the input variables are furnace temperature, power of halogen lamps, and alternating magnetic field. The degree of ion activation was evaluated as a function of processing variables, using Hall effect measurements and Raman spectroscopy. The main effects were estimated to be furnace temperature and RTA power in increasing conductivity, explained by recrystallization of doped ions and change of an amorphous Si into a crystalline Si lattice. The ion activation using rapid thermal annealing is proven to be a highly efficient process in low temperature polycrystalline Si technology.

• Journal of the Korean institute of surface engineering
• /
• v.27 no.2
• /
• pp.83-90
• /
• 1994

We have investigated the mechanism for the abnormal oxide growth occuring during oxidation of the crystalline tungsten silicide. TEM and XPS analysis reveal the abnormaly grown oxide layer consisting of crystalline $Wo_3$ and amorphous $SiO_2$. The presence of crystalline $Wo_3$ provides a rapid diffusion of oxygen through the oxide layer. The abnormal oxide growth is mainly due to the poor quality of initial oxide layer growth on tungsten silicide. Two species such as tungsten and silicon from decomposition fo tungsten silicide as well as silicon supplied from the underlying polysilicon are the main contributors sto abnormal oxide forma-tion. Consequently, the abnormal oxidation results in the disintegration of tungsten silicide and thinning of polysilicon as well.

• Korean Journal of Materials Research
• /
• v.20 no.6
• /
• pp.289-293
• /
• 2010

Silicon quantum dots (Si QDs) in a superlattice for high efficiency tandem solar cells were fabricated by magnetron rf sputtering and their characteristics were investigated. SiC/$Si_{1-x}C_x$ superlattices were deposited by co-sputtering of Si and C targets and annealed at $1000^{\circ}C$ for 20 minutes in a nitrogen atmosphere. The Si QDs in Si-rich layers were verified by transmission electron microscopy (TEM) and X-ray diffraction. The size of the QDs was observed to be 3-6 nm through high resolution TEM. Some crystal Si and -SiC peaks were clearly observed in the grazing incident X-ray diffractogram. Raman spectroscopy in the annealed sample showed a sharp peak at $516\;cm^{-1}$ which is an indication of Si QDs. Based on the Raman shift the size of the QD was estimated to be 4-6 nm. The volume fraction of Si crystals was calculated to be about 33%. The change of the FT-IR absorption spectrum from a Gaussian shape to a Lorentzian shape also confirmed the phase transition from an amorphous phase before annealing to a crystalline phase after annealing. The optical absorption coefficient also decreased, but the optical band gap increased from 1.5 eV to 2.1 eV after annealing. Therefore, it is expected that the optical energy gap of the QDs can be controlled with growth and annealing conditions.

• Korean Journal of Materials Research
• /
• v.11 no.7
• /
• pp.556-561
• /
• 2001

We prepared a new a SOS(silicon-on-silicide) wafer pair which is consisted of Si(100)/1000$\AA$-NiSi Si (100) layers. SOS can be employed in MEMS(micro- electronic-mechanical system) application due to low resistance of the NiSi layer. A thermally evaporated $1000\AA$-thick Ni/Si wafer and a clean Si wafer were pre-mated in the class 100 clean room, then annealed at $300~900^{\circ}C$ for 15hrs to induce silicidation reaction. SOS wafer pairs were investigated by a IR camera to measure bonded area and probed by a SEM(scanning electron microscope) and TEM(transmission electron microscope) to observe cross-sectional view of Si/NiSi. IR camera observation showed that the annealed SOS wafer pairs have over 52% bonded area in all temperature region except silicidation phase transition temperature. By probing cross-sectional view with SEM of magnification of 30,000, we found that $1000\AA$-thick uniform NiSi layer was formed at the center area of bonded wafers without void defects. However we observed debonded area at the edge area of wafers. Through TEM observation, we found that $10-20\AA$ thick amourphous layer formed between Si surface and NiSix near the counter part of SOS. This layer may be an oxide layer and lead to degradation of bonding. At the edge area of wafers, that amorphous layer was formed even to thickness of $1500\AA$ during annealing. Therefore, to increase bonding area of Si NiSi ∥ Si wafer pairs, we may lessen the amorphous layers.

• Transactions on Electrical and Electronic Materials
• /
• v.9 no.1
• /
• pp.28-32
• /
• 2008

Hydrogenated microcrystalline silicon(${\mu}c$-Si:H) films were prepared using inductively coupled plasma chemical vapor deposition(ICP-CVD) method, electrical and optical properties of these films were studied as a function of silane concentration. And then, effect of $PH_3\;and\;B_2H_6$ addition on their electrical properties was also investigated for solar cell application. Characterization of these films from X-ray diffraction revealed that the conductive film exists in microcrystalline phase embedded in an amorphous network. At $PH_3/SiH_4$ gas ratio of $0.9{\times}10^{-3}$, dark conductivity has a maximum value of ${\sim}18.5S/cm$ and optical bandgap also a maximum value of ${\sim}2.39eV$. Boron-doped ${\mu}c$-Si:H films, satisfied with p-layer of solar cell, could be obtained at ${\sim}10^{-2}\;of\;B_2H_6/SiH_4$.

• Journal of Information Display
• /
• v.7 no.3
• /
• pp.1-4
• /
• 2006

2.22-inch qVGA $(240{\times}320)$ amorphous silicon thin film transistor liquid active matrix crystal display (a-Si TFT-AMLCD) panel has been successfully demonstrated employing a 2.5 um fine-patterning technology by a wet etch process. Higher resolution 2.22-inch qVGA LCD panel with an aperture ratio of 58% can be fabricated as the 2.5 um fine pattern formation technique is integrated with high thermal photo-resist (PR) development. In addition, a novel concept of unique a-Si TFT process architecture, which is advantageous in terms of reliability, was proposed in the fabrication of 2.22-inch qVGA LCD panel. Overall results show that the 2.5 um fine-patterning is a considerably significant technology to obtain higher aperture ratio for higher resolution a-Si TFT-LCD panel realization.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2007.08a
• /
• pp.257-260
• /
• 2007

Hydrogenated amorphous silicon thin film transistors were fabricated on a flexible metal substrate. A negative voltage at a floated gate can be induced by a negative substrate bias through a capacitor between the substrate and gate electrode. This can recover the shifted-threshold voltage to an original value.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2013.02a
• /
• pp.230-230
• /
• 2013

In amorphous or microcrystalline thin-film silicon solar cells, p-i-n structure is used instead of p/n junction structure as in wafer-based Si solar cells. Hence, these p-i-n structured solar cells inevitably consist of many interfaces and the cell efficiency critically depends on the effective control of these interfaces. In this study, in-situ plasma treatment process of the interfaces was developed to improve the efficiency of a-Si:H solar cell. The p-i-n cell was deposited using a single-chamber VHF-PECVD system, which was driven by a pulsed-RF generator at 80 MHz. In order to solve the cross-contamination problem of p-i layer, high RF power was applied without supplying SiH4 gas after p-layer deposition, which effectively cleaned B contamination inside chamber wall from p-layer deposition. In addition to the p-i interface control, various interface control techniques such as thin layer of TiO2 deposition to prevent H2 plasma reduction of FTO layer, multiple applications of thin i-layer deposition and H2 plasma treatment, H2 plasma treatment of i-layer prior to n-layer deposition, etc. were developed. In order to reduce the reflection at the air-glass interface, anti-reflective SiO2 coating was also adopted. The initial solar cell efficiency over 11% could be achieved for test cell area of 0.2 $cm^2$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.06a
• /
• pp.37-37
• /
• 2008

Hydrogenated nanocrystalline Si (nc-Si:H) thin films were prepared by plasma enhanced chemical vapor deposition (PECVD). The films were deposited with a radio frequency power of 100 W, while substrates were exposed to direct current (DC) biases in the range from 0 to -400 V. The effects of the DC bias on the formation of nanoscale Si crystallites in the films and on their optical characteristics were investigated. The size of the Si crystallites in the films ranges from ~ 1.9 to ~ 4.1 nm. The relative fraction of the crystallites in the films reached up ~ 56.5 % when the DC bias of -400 V was applied. Based on the variation in the structural, chemical, and optical features of the films with DC bias voltages, a model for the formation of nanostructures of the nc-Si:H films prepared by PECVD was suggested. This model can be utilized to understand the evolution in the size and relative fraction of the nanocrystallites as well as the amorphous matrix in the nc-Si:H films.

• Proceedings of the KIEE Conference
• /
• 1996.07c
• /
• pp.1582-1584
• /
• 1996

The polycrystalline silicon thin film transistors (poly-Si TFT) are the most promising candidate for active matrix liquid crystal displays (AMLCD) for their high mobilities and current driving capabilities. The leakage current of the poly-Si TFT is much higher than that of the amorphous-Si TFT, thus larger storage capacitance is required which reduces the aperture ratio fur the pixel. The offset gated poly-Si TFTs have been widely investigated in order to reduce the leakage current. The conventional method for fabricating an offset device may require additional mask and photolithography process step, which is inapplicable for self-aligned source/drain ion implantation and rather cost inefficient. Due to mis-alignment, offset devices show asymmetric transfer characteristics as the source and drain are switched. We have proposed and fabricated a new offset poly-Si TFT by applying photoresist reflow process. The new method does not require an additional mask step and self-aligned ion implantation is applied, thus precise offset length can be defined and source/drain symmetric transfer characteristics are achieved.