• Title/Summary/Keyword: algorithm of critical Path

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An implementation of 2D/3D Complex Optical System and its Algorithm for High Speed, Precision Solder Paste Vision Inspection (솔더 페이스트의 고속, 고정밀 검사를 위한 이차원/삼차원 복합 광학계 및 알고리즘 구현)

  • 조상현;최흥문
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.41 no.3
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    • pp.139-146
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    • 2004
  • A 2D/3D complex optical system and its vision inspection algerian is proposed and implemented as a single probe system for high speed, precise vision inspection of the solder pastes. One pass un length labeling algorithm is proposed instead of the conventional two pass labeling algorithm for fast extraction of the 2D shape of the solder paste image from the recent line-scan camera as well as the conventional area-scan camera, and the optical probe path generation is also proposed for the efficient 2D/3D inspection. The Moire interferometry-based phase shift algerian and its optical system implementation is introduced, instead of the conventional laser slit-beam method, for the high precision 3D vision inspection. All of the time-critical algorithms are MMX SIMD parallel-coded for further speedup. The proposed system is implemented for simultaneous 2D/3D inspection of 10mm${\times}$10mm FOV with resolutions of 10 ${\mu}{\textrm}{m}$ for both x, y axis and 1 ${\mu}{\textrm}{m}$ for z axis. Experiments conducted on several nBs show that the 2D/3D inspection of an FOV, excluding an image capturing, results in high speed of about 0.011sec/0.01sec, respectively, after image capturing, with $\pm$1${\mu}{\textrm}{m}$ height accuracy.

GIS-Based Design Flood Estimation of Ungauged Watershed (논문 - GIS기반의 미계측 유역 설계홍수량 산정)

  • Hong, Seong-Min;Jung, In-Kyun;Park, Jong-Yoon;Lee, Mi-Seon;Kim, Seong-Joon
    • KCID journal
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    • v.18 no.2
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    • pp.87-100
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    • 2011
  • This study is to delineate the watershed hydrological parameters such as area, slope, rain gauge weight, NRCS-CN and time of concentration (Tc) by using the Geographic Information Sytem (GIS) technique, and estimation of design flood for an ungauged watershed. Especially, we attempted to determine the Tc of ungauged watershed and develop simple program using the cell-based algorithm to calculates upstream or downstream flow time along a flow path for each cell. For a $19km^2$ watershed of tributary of Nakdong river (Seupmoon), the parameters including flow direction, flow accumulation, watershed boundary, stream network and Tc map were extracted from 30m Agreeburn DEM (Digital Elevation Model) and landcover map. And NRCS-CN was extracted from 30m landcover map and soil map. Design rainfall estimation for two rainfall gauge which are Sunsan and Jangcheon using FARD2006 that developed by National Institute for Disaster Prevention (NIDP). Using the parameters as input data of HEC-l model, the design flood was estimated by applying Clark unit hydrograph method. The results showed that the design flood of 50 year frequency of this study was $8m^3/sec$ less than that of the previous fundamental plan in 1994. The value difference came from the different application of watershed parameter, different rainfall distribution (Huff quartile vs. Mononobe) and critical durations. We could infer that the GIS-based parameter preparation is more reasonable than the previous hand-made extraction of watershed parameters.

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Design of AES Cryptographic Processor with Modular Round Key Generator (모듈화된 라운드 키 생성회로를 갖는 AES 암호 프로세서의 설계)

  • 최병윤;박영수;전성익
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.12 no.5
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    • pp.15-25
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    • 2002
  • In this paper a design of high performance cryptographic processor which implements AES Rijndael algorithm is described. To eliminate performance degradation due to round-key computation delay of conventional processor, the on-the-fly precomputation of round key based on modified round structure is adopted. And on-the-fly round key generator which supports 128, 192, and 256-bit key has modular structure. The designed processor has iterative structure which uses 1 clock cycle per round and supports three operation modes, such as ECB, CBC, and CTR mode which is a candidate for new AES modes of operation. The cryptographic processor designed in Verilog-HDL and synthesized using 0.251$\mu\textrm{m}$ CMOS cell library consists of about 51,000 gates. Simulation results show that the critical path delay is about 7.5ns and it can operate up to 125Mhz clock frequency at 2.5V supply. Its peak performance is about 1.45Gbps encryption or decryption rate under 128-bit key ECB mode.

Energy-efficient Routing in MIMO-based Mobile Ad hoc Networks with Multiplexing and Diversity Gains

  • Shen, Hu;Lv, Shaohe;Wang, Xiaodong;Zhou, Xingming
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.9 no.2
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    • pp.700-713
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    • 2015
  • It is critical to design energy-efficient routing protocols for battery-limited mobile ad hoc networks, especially in which the energy-consuming MIMO techniques are employed. However, there are several challenges in such a design: first, it is difficult to characterize the energy consumption of a MIMO-based link; second, without a careful design, the broadcasted RREP packets, which are used in most energy-efficient routing protocols, could flood over the networks, and the destination node cannot decide when to reply the communication request; third, due to node mobility and persistent channel degradation, the selected route paths would break down frequently and hence the protocol overhead is increased further. To address these issues, in this paper, a novel Greedy Energy-Efficient Routing (GEER) protocol is proposed: (a) a generalized energy consumption model for the MIMO-based link, considering the trade-off between multiplexing and diversity gains, is derived to minimize link energy consumption and obtain the optimal transmit model; (b) a simple greedy route discovery algorithm and a novel adaptive reply strategy are adopted to speed up path setup with a reduced establishment overhead; (c) a lightweight route maintenance mechanism is introduced to adaptively rebuild the broken links. Extensive simulation results show that, in comparison with the conventional solutions, the proposed GEER protocol can significantly reduce the energy consumption by up to 68.74%.

Implementation of RSA modular exponentiator using Division Chain (나눗셈 체인을 이용한 RSA 모듈로 멱승기의 구현)

  • 김성두;정용진
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.12 no.2
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    • pp.21-34
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    • 2002
  • In this paper we propos a new hardware architecture of modular exponentiation using a division chain method which has been proposed in (2). Modular exponentiation using the division chain is performed by receding an exponent E as a mixed form of multiplication and addition with divisors d=2 or $d=2^I +1$ and respective remainders r. This calculates the modular exponentiation in about $1.4log_2$E multiplications on average which is much less iterations than $2log_2$E of conventional Binary Method. We designed a linear systolic array multiplier with pipelining and used a horizontal projection on its data dependence graph. So, for k-bit key, two k-bit data frames can be inputted simultaneously and two modular multipliers, each consisting of k/2+3 PE(Processing Element)s, can operate in parallel to accomplish 100% throughput. We propose a new encoding scheme to represent divisors and remainders of the division chain to keep regularity of the data path. When it is synthesized to ASIC using Samsung 0.5 um CMOS standard cell library, the critical path delay is 4.24ns, and resulting performance is estimated to be abort 140 Kbps for a 1024-bit data frame at 200Mhz clock In decryption process, the speed can be enhanced to 560kbps by using CRT(Chinese Remainder Theorem). Futhermore, to satisfy real time requirements we can choose small public exponent E, such as 3,17 or $2^{16} +1$, in encryption and verification process. in which case the performance can reach 7.3Mbps.

Integration of Space Syntax Theory and Logit Model for Walkability Evaluation in Urban Pedestrian Networks (도시 보행네트워크의 보행성 평가를 위한 공간구문론과 Logit 모형의 통합방안)

  • Kim, Jong Hyung;Lee, Mee Young
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.15 no.5
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    • pp.62-70
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    • 2016
  • Ensuring walkability in a city where pedestrians and vehicles coexist is an issue of critical importance. The relative relationship between vehicle transit and walkability improvements complicates the evaluation of walkability, which thus necessitates the formation of a quantitative standard by which a methodological measurement of walkability can be achieved inside the pedestrian network. Therefore, a model is determined whereby quantitative indices such as, but not limited to, experiences of accessibility, mobility, and convenience within the network are estimated. This research proposes the integration of space syntax theory and the logit path choice model in the evaluation of walkability. Space syntax theory assesses adequacy of the constructed pedestrian network through calculation of the link integration value, while the logit model estimates its safety, mobility, and accessibility using probability. The advantage of the integrated model hence lies in its ability to sufficiently reflect such evaluation measures as the integration value, mobility convenience, accessibility potential, and safety experienced by the demand in a quantitative manner through probability computation. In this research, the Dial Algorithm is used to arrive at a solution to the logit model. This process requires that the physical distance of the pedestrian network and the perceptive distance of space syntax theory be made equivalent. In this, the research makes use of network expansion to reflect wait times. The evaluation index calculated through the integrated model is reviewed and using the results of this sample network, the applicability of the model is assessed.

A Design of Pipelined Adaptive Decision-Feedback Equalized using Delayed LMS and Redundant Binary Complex Filter Structure (Delayed LMS와 Redundant Binary 복소수 필터구조를 이용한 파이프라인 적응 결정귀환 등화기 설계)

  • An, Byung-Gyu;Lee, Jong-Nam;Shin, Kyung-Wook
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.12
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    • pp.60-69
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    • 2000
  • This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer(PADFE) using a 0.25-${\mu}m$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stages are inserted into the critical path of the ADFE by using delayed least-mean-square(DLMS) algorithm. Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width, and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The single-chip PADFE contains about 205,000 transistors on an area of about $1.96\times1.35-mm^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW. Test results show that the fabricated chip works functionally well.

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A 200-MHz@2.5V 0.25-$\mu\textrm{m}$ CMOS Pipelined Adaptive Decision-Feedback Equalizer (200-MHz@2.5-V 0.25-$\mu\textrm{m}$ CMOS 파이프라인 적응 결정귀환 등화기)

  • 안병규;이종남;신경욱
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2000.05a
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    • pp.465-469
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    • 2000
  • This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer (PADFE) using a 0.25-${\mu}{\textrm}{m}$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stage are inserted into the critical path of the ADFE by using delayed least-mean-square (DLMS) algorithm Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The singl-chip PADFE contains about 205,000 transistors on an area of about 1.96$\times$1.35-$\textrm{mm}^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW.

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Development of Intelligent ATP System Using Genetic Algorithm (유전 알고리듬을 적용한 지능형 ATP 시스템 개발)

  • Kim, Tai-Young
    • Journal of Intelligence and Information Systems
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    • v.16 no.4
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    • pp.131-145
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    • 2010
  • The framework for making a coordinated decision for large-scale facilities has become an important issue in supply chain(SC) management research. The competitive business environment requires companies to continuously search for the ways to achieve high efficiency and lower operational costs. In the areas of production/distribution planning, many researchers and practitioners have developedand evaluated the deterministic models to coordinate important and interrelated logistic decisions such as capacity management, inventory allocation, and vehicle routing. They initially have investigated the various process of SC separately and later become more interested in such problems encompassing the whole SC system. The accurate quotation of ATP(Available-To-Promise) plays a very important role in enhancing customer satisfaction and fill rate maximization. The complexity for intelligent manufacturing system, which includes all the linkages among procurement, production, and distribution, makes the accurate quotation of ATP be a quite difficult job. In addition to, many researchers assumed ATP model with integer time. However, in industry practices, integer times are very rare and the model developed using integer times is therefore approximating the real system. Various alternative models for an ATP system with time lags have been developed and evaluated. In most cases, these models have assumed that the time lags are integer multiples of a unit time grid. However, integer time lags are very rare in practices, and therefore models developed using integer time lags only approximate real systems. The differences occurring by this approximation frequently result in significant accuracy degradations. To introduce the ATP model with time lags, we first introduce the dynamic production function. Hackman and Leachman's dynamic production function in initiated research directly related to the topic of this paper. They propose a modeling framework for a system with non-integer time lags and show how to apply the framework to a variety of systems including continues time series, manufacturing resource planning and critical path method. Their formulation requires no additional variables or constraints and is capable of representing real world systems more accurately. Previously, to cope with non-integer time lags, they usually model a concerned system either by rounding lags to the nearest integers or by subdividing the time grid to make the lags become integer multiples of the grid. But each approach has a critical weakness: the first approach underestimates, potentially leading to infeasibilities or overestimates lead times, potentially resulting in excessive work-inprocesses. The second approach drastically inflates the problem size. We consider an optimized ATP system with non-integer time lag in supply chain management. We focus on a worldwide headquarter, distribution centers, and manufacturing facilities are globally networked. We develop a mixed integer programming(MIP) model for ATP process, which has the definition of required data flow. The illustrative ATP module shows the proposed system is largely affected inSCM. The system we are concerned is composed of a multiple production facility with multiple products, multiple distribution centers and multiple customers. For the system, we consider an ATP scheduling and capacity allocationproblem. In this study, we proposed the model for the ATP system in SCM using the dynamic production function considering the non-integer time lags. The model is developed under the framework suitable for the non-integer lags and, therefore, is more accurate than the models we usually encounter. We developed intelligent ATP System for this model using genetic algorithm. We focus on a capacitated production planning and capacity allocation problem, develop a mixed integer programming model, and propose an efficient heuristic procedure using an evolutionary system to solve it efficiently. This method makes it possible for the population to reach the approximate solution easily. Moreover, we designed and utilized a representation scheme that allows the proposed models to represent real variables. The proposed regeneration procedures, which evaluate each infeasible chromosome, makes the solutions converge to the optimum quickly.

Cluster-based Delay-adaptive Sensor Scheduling for Energy-saving in Wireless Sensor Networks (센서네트워크에서 클러스터기반의 에너지 효율형 센서 스케쥴링 연구)

  • Choi, Wook;Lee, Yong;Chung, Yoo-Jin
    • Journal of the Korea Society for Simulation
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    • v.18 no.3
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    • pp.47-59
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    • 2009
  • Due to the application-specific nature of wireless sensor networks, the sensitivity to such a requirement as data reporting latency may vary depending on the type of applications, thus requiring application-specific algorithm and protocol design paradigms which help us to maximize energy conservation and thus the network lifetime. In this paper, we propose a novel delay-adaptive sensor scheduling scheme for energy-saving data gathering which is based on a two phase clustering (TPC). The ultimate goal is to extend the network lifetime by providing sensors with high adaptability to the application-dependent and time-varying delay requirements. The TPC requests sensors to construct two types of links: direct and relay links. The direct links are used for control and forwarding time critical sensed data. On the other hand, the relay links are used only for data forwarding based on the user delay constraints, thus allowing the sensors to opportunistically use the most energy-saving links and forming a multi-hop path. Simulation results demonstrate that cluster-based delay-adaptive data gathering strategy (CD-DGS) saves a significant amount of energy for dense sensor networks by adapting to the user delay constraints.