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The Implementation of Recording and Replaying System and Its Device Driver Programming (HDD를 이용한 저장ㆍ재생기의 구현 및 디바이스 드라이버 프로그래밍)

  • 최효정;이중호;김대진
    • Proceedings of the IEEK Conference
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    • 2003.11c
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    • pp.382-385
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    • 2003
  • Introduction of digital broadcasting service does not only mean the change of information transmission method but also the change of total broadcasting system. In past day, Television was only received one-sided information from broadcasting station, but digital broadcasting means that digital television becomes the most important means of information transmission by the introduction of new programming, lots of channels, data service, multi communication. In the age of the digital broadcasting, the recording and replay medium's interest is getting higher. The medium is able to record more than 24 hours' digital broadcasting programs without additional tapes. In this paper the recording and replay device using HDD was implemented and device driver based on linux was programmed. It has Intel PXA250 processor and hard disk is used as storage equipment. And transport Stream is saved on hard disk through PXA250's data bus. FIFO is added to solve the different saving speed and FPGA is also added to display the saved data.

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ML-Based Estimation Algorithm of Frequency Offset for $2{\times}2$ STBC-OFDM Systems

  • Lei, Ming;Zhao, Minjian;Zhong, Jie;Cai, Yunlong
    • ETRI Journal
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    • v.34 no.3
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    • pp.458-461
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    • 2012
  • In this letter, we propose a novel frequency offset estimation algorithm for space-time block code (STBC) orthogonal frequency division multiplexing systems. The algorithm mainly exploits the specific construction of STBC so that it does not need any additional pilots or sequences in the data field. The estimator is derived on the basis of the maximum likelihood theory. Simulation results show that this method can provide a significant performance improvement in terms of the estimation accuracy of the frequency offset.

Discrete Cosine Transformer with Variable-Length Basis Vector for MPEG-4 Video Codec

  • Kuroda, Ryo;Fujita, Gen;Onoye, Takao;Shirakawa, Isao
    • Proceedings of the IEEK Conference
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    • 2000.07b
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    • pp.811-814
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    • 2000
  • It this paper a VLSI architecture of the Shape-Adaptive Discrete Cosine Transform (SA-DCT) is described, which can be employed dedicatedly for MPEG-4 video codec. Adopting a fast DCT algorithm, the number of multipliers can be reduced by half in comparison with a conventional algorithm. This SA-DCT core with a small additional amount of hardware can perform the SA-Inverse DCT (SA-IDCT) by sharing multipliers and a transportation memory. The proposed SA-DCT core is integrated with 40,000 gates by using 0.35$mu$m triple-metal CMOS technology, which operates at 20 Mhz, and hence enables the realtime codec of CIF ($352{\times}288$ pixels) pictures.

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Filling and Labelling Algorithm Using Directional Information of Chain-code (체인코드의 방향정보를 이용한 Filling과 Labelling)

  • 심재창;하금숙;현기호;하영호
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.29B no.9
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    • pp.50-58
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    • 1992
  • A new algorithm for filling the interior of contours and labelling each filled region concurrently is presented. Filling is simply accomplished by inversion method. The labelling information in every scan lines is extracted directly from current direction of chain code so that the proposed algorithm needs less comparision and is more efficient. The contours are followed by two different directions, clockwise for the outer contour and counterclockwise for the inner contour to get filling and labelling information. This algorithm can be applied in case that contours are nested or regions are continous. Simulataneously the proposed algorithm can find the structure tree of object without additional post processing.

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Scalable High-quality Speech Reconstruction in Distributed Speech Recognition Environments (분산음성인식 환경에서 서버에서의 스케일러블 고품질 음성복원)

  • Yoon, Jae-Sam;Kim, Hong-Kook;Kang, Byung-Ok
    • Proceedings of the IEEK Conference
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    • 2007.07a
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    • pp.423-424
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    • 2007
  • In this paper, we propose a scalable high-quality speech reconstruction method for distributed speech recognition (DSR). It is difficult to reconstruct speech of high quality with MFCCs at the DSR server. Depending on the bit-rate available by the DSR system, we can send additional information associated with speech coding to the DSR sorrel, where the bit-rate is variable from 4.8 kbit/s to 11.4 kbit/s. The experimental results show that the speech quality reproduced by the proposed method when the bit-rate is 11.4 kbit/s is comparable with that of ITU-T G.729 under both ideal channel and frame error channel conditions while the performance of DSR is maintained to that of wireline speech recognition.

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A single-clock-driven gate driver using p-type, low-temperature polycrystalline silicon thin-film transistors

  • Kim, Kang-Nam;Kang, Jin-Seong;Ahn, Sung-Jin;Lee, Jae-Sic;Lee, Dong-Hoon;Kim, Chi-Woo;Kwon, Oh-Kyong
    • Journal of Information Display
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    • v.12 no.1
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    • pp.61-67
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    • 2011
  • A single-clock-driven shift register and a two-stage buffer are proposed, using p-type, low-temperature polycrystalline silicon thin-film transistors. To eliminate the clock skew problems and to reduce the burden of the interface, only one clock signal was adopted to the shift register circuit, without additional reference voltages. A two-stage, p-type buffer was proposed to drive the gate line load and shows a full-swing output without threshold voltage loss. The shift register and buffer were designed for the 3.31" WVGA ($800{\times}480$) LCD panel, and the fabricated circuits were verified via simulations and measurements.

3X Serial GF(2$^m$) Multiplier on Polynomial Basis

  • Moon, San-Gook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • v.9 no.1
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    • pp.928-930
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    • 2005
  • With an increasing importance of the information security issues, the efficienct calculation process in terms of finite field level is becoming more important in the Elliptic curve cryptosystems. Serial multiplication architectures are based on the Mastrovito's serial multiplier structure. In this paper, we manipulate the numerical expressions so that we could suggest a 3-times as fast as (3x) the Mastrovito's multiplier using the polynomial basis. The architecture was implemented with HDL, to be evaluated and verified with EDA tools. The implemented 3x GF (Galois Field) multiplier showed 3 times calculation speed as fast as the Mastrovito's, only with the additional partial-sum generation processing unit.

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Privacy Protection Model for Location-Based Services

  • Ni, Lihao;Liu, Yanshen;Liu, Yi
    • Journal of Information Processing Systems
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    • v.16 no.1
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    • pp.96-112
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    • 2020
  • Solving the disclosure problem of sensitive information with the k-nearest neighbor query, location dummy technique, or interfering data in location-based services (LBSs) is a new research topic. Although they reduced security threats, previous studies will be ineffective in the case of sparse users or K-successive privacy, and additional calculations will deteriorate the performance of LBS application systems. Therefore, a model is proposed herein, which is based on geohash-encoding technology instead of latitude and longitude, memcached server cluster, encryption and decryption, and authentication. Simulation results based on PHP and MySQL show that the model offers approximately 10× speedup over the conventional approach. Two problems are solved using the model: sensitive information in LBS application is not disclosed, and the relationship between an individual and a track is not leaked.

Design and Implementation of a Mail Browser that can control Data-Flow on the Web (Web에서 데이터 흐름제어가 가능한 Mail Browser의 설계 및 구현)

  • Park, Gyu-Seok;Kim, Seong-Hu
    • The Transactions of the Korea Information Processing Society
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    • v.6 no.10
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    • pp.2752-2763
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    • 1999
  • On account of the text based mail system has it's limit to support multimedia applications, GUI based mail system platform was developed to control document flow and automatize information process. The existing mail systems's to transmit data must need additional functions to automate document flow control. The platform of document flow control is deeply related to EDMAS(Electronic document Management System), workflow, Electronic Banking, DMS(Document Management System) automation, so it needs an ability to control proper data and document correctly. To resolve this problems, we are need of browser and engine to design work flow and to control documents flow. In this paper, we develope a mail browser to design document flow by follow user's requirements. This system can generate executive script code for document flow, and we add the function of workflow and process management to automatize the document flow in this system, and then we implement this Data flow engine.

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The Problem of the e-value of InterPro to find additional domains in Domain Combination (InterPro의 e-value 조정을 통한 신규 도메인 발견 접근 방식의 문제점)

  • Hur, Hee-Young;Han, Dong-Soo
    • Proceedings of the Korean Information Science Society Conference
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    • 2006.10a
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    • pp.17-21
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    • 2006
  • 도메인 기반 단백질 상호작용 예측 기법은 지난 몇 년 동안 활발히 연구되어 왔다. 도메인 기반 접근 방법 중에서도 도메인 조합 기반 단백질 상호작용 가능성 순위 부여 기법은 예측 정확도면에서 다른 기법보다 월등한 결과를 보여주고 있다. 그러나 학습 집단을 사용하는 특징 때문에 전체 도메인 정보를 이용할 수 없는 단점이 있다. 또한, 이 시스템은 도메인 정보가 부족하여 다른 기능을 하는 단백질이라도 같은 도메인 정보를 보여주기 때문에 예측 시스템의 결점을 드러내고 있다. 도메인 조합 기반 단백질 상호작용 가능성 순위 부여 기법은 InterPro 데이터베이스의 도메인 정보를 기반으로 사용한다. InterProScan은 InterPro의 여러 멤버 데이터베이스의 정보를 기반으로 Sequence 분석을 하는 소프트웨어로써 검색 후 단계에서 찾아낸 결과들을 e-value를 기반으로 여과한다. 본 논문에서는 제시된 e-value를 조정 방법을 사용함으로써 단백질 내 도메인 패턴의 다양화와 기존 도메인 정보가 없던 단백질의 도메인을 새롭게 발견할 수 있으나 접근 방식의 한계가 존재함을 확인할 수 있었다.

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