• Title/Summary/Keyword: adaptive design

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Design of CMOS LC VCO with Fast AFC Technique for IEEE 802.11a/b/g Wireless LANs (IEEE 802.11a/b/g 무선 랜을 위한 고속 AFC 기법의 CMOS LC VCO의 설계)

  • Ahn Tae-Won;Yoon Chan-Geun;Moon Yong
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.9 s.351
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    • pp.17-22
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    • 2006
  • CMOS LC VCO with fast response adaptive frequency calibration (AFC) technique for IEEE 802.11a/b/g WLANs is designed in 1.8V $0.18{\mu}m$ CMOS process. The possible operation is verified for 5.8GHz band, 5.2GHz band, and 2.4GHz band using the switchable L-C resonators. To linearize its frequency-voltage gain (Kvco), optimized multiple MOS varactor biasing tecknique is used. In order to operate in each band frequency range with reduced VCO gain, 4-bit digitally controlled switched- capacitor bank is used and a wide-range digital logic quadricorrelator (WDLQ) is implemented for fast frequency detector.

Design of a high-speed DFE Equaliser of blind algorithm using Error Feedback (Error Feedback을 이용한 blind 알고리즘의 고속 DFE Equalizer의 설계)

  • Hong Ju H.;Park Weon H.;Sunwoo Myung H.;Oh Seong K.
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.42 no.8 s.338
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    • pp.17-24
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    • 2005
  • This paper proposes a Decision Feedback Equalizer (DFT) with an error feedback filter for blind channel equalization. The proposed equalizer uses Least Mean Square(LMS) Algorithm and Multi-Modulus Algorithm (MMA), and has been designed for 64/256 QAM constellations. The existing MMA equalizer uses either two transversal filters or feedforward and feedback filers, while the proposed equalizer uses feedforward, feedback and error feedback filters to improve the channel adaptive performance and to reduce the number of taps. The proposed equalizer has been simulated using the $SPW^{TM}$ tool and it shows performance improvement. It has been modeled by VHDL and logic synthesis has been performed using the $0.25\;\mu m$ Faraday CMOS standard cell library. The total number of gates is about 190,000 gates. The proposed equalizer operates at 15 MHz. In addition, FPGA vertification has been performed using FPGA emulation board.

A New H.264/AVC CAVLC Parallel Decoding Circuit (새로운 H.264/AVC CAVLC 고속 병렬 복호화 회로)

  • Yeo, Dong-Hoon;Shin, Hyun-Chul
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.11
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    • pp.35-43
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    • 2008
  • A new effective parallel decoding method has been developed for context-based adaptive variable length codes. In this paper, several new design ideas have been devised for scalable parallel processing, less area, and less power. First, simplified logical operations instead of memory look-ups are used for fast low power operations. Second the codes are grouped based on their lengths for efficient logical operation. Third, up to M bits of input are simultaneously analyzed. For comparison, we have designed the logical operation based parallel decoder for M=8 and a typical conventional method based decoder. High speed parallel decoding is possible with our method. For similar decoding rates (1.57codes/cycle for M=8), our new approach uses 46% less area than the typical conventional method.

Design of a High-speed Decision Feedback Equalizer using the Constant-Modulus Algorithm (CMA 알고리즘을 이용한 고속 DFE 등화기 설계)

  • Jeon, Yeong-Seop;;Kim, Gyeong-Ho
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.39 no.4
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    • pp.173-179
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    • 2002
  • This paper describes an equalizer using the DFE (Decision Feedback Equalizer) structure, CMA (Constant Modulus Algorithm) and LMS (Least Mean Square) algorithms. The DFE structure has better channel adaptive performance and lower BER than the transversal structure. The proposed equalizer can be used for 16/64 QAM modems. We employ high speed multipliers, square logics and many CSAs (Carry Save Adder) for high speed operations. We have developed floating-point models and fixed-point models using the COSSAP$\^$TM/ CAD tool and developed VHDL filter. The proposed equalizer shows low BER in multipath fading channel. We have performed models. From the simulation results, we employ a 12 tap feedback filter and a 8 tap feedforward logic synthesis using the SYNOPSYS$\^$TM/ CAD tool and the SAMSUNG 0.5$\mu\textrm{m}$ standard cell library (STD80) and verified function and timing simulations. The total number of gates is about 130,000.

High Performance Speed Control of IPMSM with LM-FNN Controller (LM-FNN 제어기에 의한 IPMSM의 고성능 속도제어)

  • Nam, Su-Myeong;Choi, Jung-Sik;Chung, Dong-Hwa
    • The Transactions of the Korean Institute of Power Electronics
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    • v.11 no.1
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    • pp.29-37
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    • 2006
  • Precise control of interior permanent magnet synchronous motor(IPMSM) over wide speed range is an engineering challenge. This paper considers the design and implementation of novel technique of high performance speed control for IPMSM using learning mechanism-fuzzy neural network(LM-FNN) and ANN(artificial neural network) control. The hybrid combination of neural network and fuzzy control will produce a powerful representation flexibility md numerical processing capability. Also, this paper proposes speed control of IPMSM using LM-FNN and estimation of speed using artificial neural network controller. The back propagation neural network technique is used to provide a real time adaptive estimation of the motor speed. 'The error between the desired state variable and the actual one is back-propagated to adjust the rotor speed, so that the actual state variable will coincide with the desired one. The back propagation mechanism is easy to derive and the estimated speed tracks precisely the actual motor speed. Analysis results to verify the effectiveness of the new hybrid intelligent control proposed in this paper.

The Design of Repeated Motion on Adaptive Block Matching Algorithm in Real-Time Image (실시간 영상에서 반복적인 움직임에 적응한 블록정합 알고리즘 설계)

  • Kim Jang-Hyung;Kang Jin-Suk
    • Journal of Korea Multimedia Society
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    • v.8 no.3
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    • pp.345-354
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    • 2005
  • Since motion estimation and motion compensation methods remove the redundant data to employ the temporal redundancy in images, it plays an important role in digital video compression. Because of its high computational complexity, however, it is difficult to apply to high-resolution applications in real time environments. If we have a priori knowledge about the motion of an image block before the motion estimation, the location of a better starting point for the search of an exact motion vector can be determined to expedite the searching process. In this paper presents the motion detection algorithm that can run robustly about recusive motion. The motion detection compares and analyzes two frames each other, motion of whether happened judge. Through experiments, we show significant improvements in the reduction of the computational time in terms of the number of search steps without much quality degradation in the predicted image.

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A Design of Low-Power Wideband Bipolar Current Conveyor (CCII) and Its Application to Universal Instrumentation Amplifiers (저전력 광대역 바이폴라 전류 콘베이어(CCII)와 이를 이용한 유니버셜 계측 증폭기의 설계)

    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.5
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    • pp.143-152
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    • 2004
  • A novel low-power wideband bipolar second-generation current conveyors(CCIIs) and its application to universal instrumentation amplifier(UIA) were proposed. The CCII for accuracy voltage or current transfer characteristics and low current input impedance adopted adaptive current bias circuit into conventional class Ab CCII. The UIA consists of only two CCIIs and four resistors. Three instrumentation function of the UIA can be realized by selection of input signals and resistors. The simulation results show that the CCII has input impedance of 2.0$\Omega$ and the voltage gain of 60㏈ for frequency range from 0 to 50KHz when used as a voltage amplifier. The CCII has also good characteristics of current follower for current range from -100㎃ to +100㎃. The simulation results show that the UIA has three instrumentation amplifier functions without resistor matching. The UIA has the voltage gain of 40㏈ for frequency range from 0 to 100KHz when used as a fully-differential instrumentation amplifier. The power dissipations of the CCII and the UIA are 0.75㎽ and 1.5㎽ at supply voltage of $\pm$2.5V, respectively.

Residual Vibration Control of High Speed Take-out Robot Used for Handling of Injection Mold Plastic Part (고속운동 플라스틱 금형사출 부품 취출 로봇의 잔류진동 제어)

  • Rhim, Sung-Soo;Park, Joo-Han
    • Journal of the Korean Society for Precision Engineering
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    • v.28 no.9
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    • pp.1025-1031
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    • 2011
  • Take-out robots used for handling of the plastic parts manufactured with the injection mold are usually the gantry type that consists of long and thin links, The performance of the take-out robot is determined by the speed of the motion and the positioning accuracy to grab the part out of the mold, As the speed of the robot increases the flexure in the links of the take-out robot becomes more significant and it results in more residual vibration, The residual vibration deteriorates the positioning accuracy and compels the operator to slow down the motion of the robot. The typical method to reduce the vibration in the robot requires stiffening the links and/or slowing down the robot, Vibration control could achieve the desired performance without increasing the manufacturing cost or the operation cost that would be incurred otherwise, Considering the point-to-point nature of the task to be performed by the take-out robot the time-delay command (or input) shaping filter approach would be the most effective control method to be adopted among a few available control schemes. In this paper a direct adaptive command shaping filter (ACSF) algorithm has been modified and applied to design the optimal command shaping filters for various configuration of the take-out robot. Optimal filters designed by ACSF algorithm have been implemented on a take-out robot and the effectiveness of the designed filters in terms of vibration suppression has been verified for multiple positions of the robot.

Efficiency Optimization Control of SynRM with Hybrid Artificial Intelligent Controller (하이브리드 인공지능 제어기에 의한 SynRM의 효율 최적화 제어)

  • Chung, Dong-Hwa;Choi, Jung-Sik;Ko, Jae-Sub
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.21 no.5
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    • pp.1-9
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    • 2007
  • This paper is proposed an efficiency optimization control algorithm for a synchronous reluctance motor which minimizes the coner and iron losses. The design of the speed controller based on adaptive fuzzy-neural networks(AFNN) controller that is implemented using fuzzy control and neural networks. There exists a variety of combinations of d and q-axis current which provide a specific motor torque. The objective of the efficiency optimization controller is to seek a combination of d and q-axis current components, which provides minimum losses at a certain operating point in steady state. The proposed algorithm allows the electromagnetic losses in variable speed and torque drives to be reduced while keeping good torque control dynamics. The control performance of the hybrid artificial intelligent controller is evaluated by analysis for various operating conditions. Analysis results are presented to show the validity of the proposed algorithm.

Design of Variable Gain Low Noise Amplifier with Memory Effects Feedback for 5.2 GHz Band (5.2 GHz 대역에서 동작하는 기억 기능 특성을 갖는 궤환 회로를 이용한 변환 이득 저잡음 증폭기 설계)

  • Lee, Won-Tae;Jeong, Ji-Chai
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.21 no.1
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    • pp.53-60
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    • 2010
  • This paper presents a novel gain control system composed of a feedback circuit, Two stage Low Noise Amplifier (LNA) using 0.18 um CMOS technology for 5.2 GHz. The feedback circuit consists of the seven function blocks: peak detector, comparator, ADC, IVE(Initial Voltage Elimination) circuit, switch, storage, and current controller. We focus on detecting signal and designing storage circuit that store the previous state. The power consumption of the feedback circuit in the system can be reduced without sacrificing the gain by inserting the storage circuit. The adaptive front-end system with the feedback circuit exhibits 11.39~22.74 dB gain, and has excellent noise performance at high gain mode. Variable gain LNA consumes 5.68~6.75 mW from a 1.8 V supply voltage.