• Title/Summary/Keyword: adaptive circuit

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Research on Speed Estimation Method of Induction Motor based on Improved Fuzzy Kalman Filtering

  • Chen, Dezhi;Bai, Baodong;Du, Ning;Li, Baopeng;Wang, Jiayin
    • Journal of international Conference on Electrical Machines and Systems
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    • v.3 no.3
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    • pp.272-275
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    • 2014
  • An improved fuzzy Kalman filtering speed estimation scheme was proposed by means of measuring stator side voltage and current value based on vector control state equation of induction motor. The designed fuzzy adaptive controller conducted recursive online correction of measurement noise covariance matrix by monitoring the ratio of theory residuals and actual residuals to make it approach real noise level gradually, allowing the filter to perform optimal estimation to improve estimation accuracy of EKF. Meanwhile, co-simulation scheme based on MATLAB and Ansoft was proposed in order to improve simulation accuracy. Field-circuit coupling problems of induction motor under the action of vector control were solved and the parameter optimization accuracy was improved dramatically. The simulation and experimental results show that this algorithm has a strong ability to inhibit the random measurement noise. It is able to estimate motor speed accurately, and has superior static and dynamic characteristics.

A Continuous-time Equalizer adopting a Clock Loss Tracking Technique for Digital Display Interface(DDI) (클록 손실 측정 기법을 이용한 DDI용 연속 시간 이퀄라이저)

  • Kim, Kyu-Young;Kim, Gil-Su;Shon, Kwan-Su;Kim, Soo-Won
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.2
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    • pp.28-33
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    • 2008
  • This paper presents a continuous-time equalizer adopting a clock loss tracking technique for digital display interface. This technique uses bottom hold circuit to detect the incoming clock loss. The generated loss signal is directly fed to equalizer filters, building adaptive feed-forward loops which contribute the stability of the system. The design was done in $0.18{\mu}m$ CMOS technology. Experimental results summarize that eye-width of minimum 0.7UI is achieved until -33dB channel loss at 1.65Gbps. The average power consumption of the equalizer is a maximum 10mW, a very low value in comparison to those of previous researches, and the effective area is $0.127mm^2$.

Single-Phase Improved Auxiliary Resonant Snubber Inverter that Reduces the Auxiliary Current and THD

  • Zhang, Hailin;Kou, Baoquan;Zhang, He;Zhang, Lu
    • Journal of Power Electronics
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    • v.16 no.6
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    • pp.1991-2004
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    • 2016
  • An LC filter is required to reduce the output current ripple in the auxiliary resonant snubber inverter (ARSI) for high-performance applications. However, if the traditional control method is used in the ARSI with LC filter, then unnecessary current flows in the auxiliary circuit. In addressing this problem, a novel load-adaptive control that fully uses the filter inductor current ripple to realize the soft-switching of the main switches is proposed. Compared with the traditional control implemented in the ARSI with LC filter, the proposed control can reduce the required auxiliary current, contributing to higher efficiency and DC-link voltage utilization. In this study, the detailed circuit operation in the light load mode (LLM) and the heavy load mode (HLM) considering the inductor current ripple is described. The characteristics of the improved ARSI are expressed mathematically. A prototype with 200 kHz switching frequency, 80 V DC voltage, and 8 A maximum output current was developed to verify the effectiveness of the improved ARSI. The proposed ARSI was found to successfully operate in the LLM and HLM, achieving zero-voltage switching (ZVS) of the main switches and zero-current switching (ZCS) of the auxiliary switches from zero load to full load. The DC-link voltage utilization of the proposed control is 0.758, which is 0.022 higher than that of the traditional control. The peak efficiency is 91.75% at 8 A output current for the proposed control, higher than 89.73% for the traditional control. Meanwhile, the carrier harmonics is reduced from -44 dB to -66 dB through the addition of the LC filter.

Design of Stack Monitoring System with Improved Performance (성능이 향상된 Stack Monitoring System의 설계)

  • Jang, Kyeong-Uk;Lee, Joo-Hyun;Lee, Seong-Won;Lee, Seung-Ho
    • Journal of IKEEE
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    • v.20 no.3
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    • pp.299-302
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    • 2016
  • In this paper, we designed the stack monitoring system with improved performance. To block the incoming pulse noise to the amplifier, shield and the power supply impedance are reduced and the power circuit is isolated. The control unit is developed with variable high voltage, adaptive gain, offset and threshold in order to match the scintillation detector characteristic to the apparatus. 300-1500V variable high voltage power circuit is configured applicable to various scintillation detector. Stack monitoring system with improved performance guarantee the efficiency and the reliability by considering the characteristic of various scintillation detector. Developed stack monitoring system is evaluated with certified testing equipment and shows excellent performance with respect to the uncertainty of the sensor test results.

Improving Transmission in Association with the Distance for Military Microwave Communications (군 MicroWave 통신 환경에서의 링크 거리를 고려한 전송 성능 향상 기법)

  • Youn, Jong Taek;Lim, Young Gap;Kim, Young Ho
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.39C no.11
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    • pp.1042-1049
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    • 2014
  • In Military MicroWave communication, the distance of link, availability, transmission capacity is the important point in order to design the circuit. Currently, operated by fixed modulation, in the future it will be evolved to the modulation techniques enabled to increase the transmission capacity. It would be hard to consistently guarantee the transmission quality of the high-availability because the occurrence probability of fading increase in terms of the link distance for the case of the long distance. In the case of the modulation techniques for the transmission of high-capacity, as the distance is long, a falling-off in the fade margin from the link budget analysis cause the decrease in the availability. It is difficult to provide QoS guaranteed connection. In this paper, we propose the performance improvement technique of transmission by the variable allocation of the bandwidth and the higher priority transmission technique using setting the ratio of the higher priority capacity in association with the distance of link. Also we suggest the alternative of the calculation for channel transmission capacity to design the circuit.

A Stable Multilevel Partitioning Algorithm for VLSI Circuit Designs Using Adaptive Connectivity Threshold (가변적인 연결도 임계치 설정에 의한 대규모 집적회로 설계에서의 안정적인 다단 분할 방법)

  • 임창경;정정화
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.35C no.10
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    • pp.69-77
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    • 1998
  • This paper presents a new efficient and stable multilevel partitioning algorithm for VLSI circuit design. The performance of multilevel partitioning algorithms that are proposed to enhance the performance of previous iterative-improvement partitioning algorithms for large scale circuits, depend on choice of construction methods for partition hierarchy. As the most of previous multilevel partitioning algorithms forces experimental constraints on the process of hierarchy construction, the stability of their performances goes down. The lack of stability causes the large variation of partition results during multiple runs. In this paper, we minimize the use of experimental constraints and propose a new method for constructing partition hierarchy. The proposed method clusters the cells with the connection status of the circuit. After constructing the partition hierarchy, a partition improvement algorithm, HYIP$^{[11]}$ using hybrid bucket structure, unclusters the hierachy to get partition results. The experimental results on ACM/SIGDA benchmark circuits show improvement up to 10-40% in minimum outsize over the previous algorithm $^{[3] [4] [5] [8] [10]}$. Also our technique outperforms ML$^{[10]}$ represented multilevel partition method by about 5% and 20% for minimum and average custsize, respectively. In addition, the results of our algorithm with 10 runs are better than ML algorithm with 100 runs.

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3-Dimensional Numerical Analysis of Deep Depletion Buried Channel MOSFETs and CCDs

  • Kim Man-Ho
    • Journal of Electrical Engineering and Technology
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    • v.1 no.3
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    • pp.396-405
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    • 2006
  • The visual analysis of buried channel (Be) devices such as buried channel MOSFETs and CCDs (Charge Coupled Devices) is investigated to give better understanding and insight for their electrical behaviours using a 3-dimensional (3-D) numerical simulation. This paper clearly demonstrates the capability of the numerical simulation of 'EVEREST' for characterising the analysis of a depletion mode MOSFET and BC CCD, which is a simulation software package of the semiconductor device. The inverse threshold and punch-through voltages obtained from the simulations showed an excellent agreement with those from the measurement involving errors of within approximately 1.8% and 6%, respectively, leading to the channel implanted doping profile of only approximately $4{\sim}5%$ error. For simulation of a buried channel CCD an advanced adaptive discretising technique was used to provide more accurate analysis for the potential barrier height between two channels and depletion depth of a deep depletion CCD, thereby reducing the CPU running time and computer storage requirements. The simulated result for the depletion depth also showed good agreement with the measurement. Thus, the results obtained from this simulation can be employed as the input data of a circuit simulator.

A Highly Linear and Efficiency Class-F Power Amplifier using PBG and application EER Structure (EER 구조의 응용과 PBG를 이용한 고효율, 고선형성 Class-F 전력 증폭기)

  • Lee, Chong-Min;Seo, Chul-Hun
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.44 no.2
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    • pp.81-86
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    • 2007
  • In this paper, the Power Added Efficiency (PAE) and linearity of class-F PA has been improved by using the PBG structure and the application of EER structure, simultaneously. The adaptive bias control circuit has been employed to improve the PAE through the application of EER structure. The PBG structure has been adapted for improving the Linearity by suppressing the harmonics on the output of amplifier. The PAE and the 3rd Inter-Modulation Distortion (IMD) has improved 34.56%, 10.66 dB, compared with those of the conventional Doherty amplifier, respectively.

Development of the speed up x-DSL extender for AM, HF rejection (공중파 제거를 위한 x-DSL 고속화 장치 개발)

  • Min, Gyung-Chan;Oh, Ho-Seuk;Kang, Jeong-Jin;Kim, Sin-Ryeong;Chang, Hark-Sin
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.8 no.6
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    • pp.9-14
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    • 2008
  • Intentional city bands and public radio frequencies could reduce the internet transmission speed on the wired lines because AM and HF band are overlapping on the xDSL up and down data steam by way of the wired transmission lines. We were designed the adaptive common mode rejection circuit with 2 way amplifier against public radio frequency. Specially our circuits were applied for power and signal lines. We could reduced the common mode rejection up to 30dB and increased the up stream speed around 1.8 times using a our developed equipments. Also it could expanded the transmission distance up to 1.7 times than old lines.

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An Advanced Coding for Video Streaming System: Hardware and Software Video Coding

  • Le, Tuan Thanh;Ryu, Eun-Seok
    • Journal of Internet Computing and Services
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    • v.21 no.4
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    • pp.51-57
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    • 2020
  • Currently, High-efficient video coding (HEVC) has become the most promising video coding technology. However, the implementation of HEVC in video streaming systems is restricted by factors such as cost, design complexity, and compatibility with existing systems. While HEVC is considering deploying to various systems with different reached methods, H264/AVC can be one of the best choices for current video streaming systems. This paper presents an adaptive method for manipulating video streams using video coding on an integrated circuit (IC) designed with a private network processor. The proposed system allows to transfer multimedia data from cameras or other video sources to client. For this work, a series of video or audio packages from the video source are forwarded to the designed IC via HDMI cable, called Tx transmitter. The Tx processes input data into a real-time stream using its own protocol according to the Real-Time Transmission Protocol for both video and audio, then Tx transmits output packages to the video client though internet. The client includes hardware or software video/audio decoders to decode the received packages. Tx uses H264/AVC or HEVC video coding to encode video data, and its audio coding is PCM format. By handling the message exchanges between Tx and the client, the transmitted session can be set up quickly. Output results show that transmission's throughput can be achieved about 50 Mbps with approximately 80 msec latency.