• 전자공학회논문지D
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• 제35D권10호
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• pp.83-90
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• 1998

MOS 캐패시터의 게이트 전극을 비정질 상태의 실리콘으로 형성하여 GOI(Gate Oxide Integrity)특성에 미치는 불순물 활성화 열처리의 효과를 조사하였다. LPCVD(Low Pressure Chemical Vapor Deposition) 방법으로 증착한 비정질 실리콘 게이트 전극은 활성화 열처리에 의하여 다결정 실리콘 상태로 구조가 변화하며, 불순물 원자의 활성화가 충분히 이루어졌다. 또한, 비정질 상태의 게이트 전극은 커다란 압축 응력(compressive stress)을 가지지만, 활성화 열처리 온도가 700℃에서 900℃로 증가함에 따라서 응력이 완화되었고 게이트 전극의 저항도 감소하는 특성을 보였다. 또한 얇은 게이트 산화막의 신뢰성 및 산화막의 계면특성은 활성화 열처리 온도에 크게 의존하고 있었다. 900℃에서 활성화 열처리를 한 경우가 700℃에서 열처리한 경우보다 산화막내에서의 전하 포획 특성이 개선되었으며, 산화막의 신뢰성이 향상되었다. 특히, TDDB 방법으로 예측한 게이트 산화막의 수명은 700℃의 열처리에서는 3×10/sup 10/초였지만, 900℃에서의 열처리에서는 2×10/sup 12/초로 현저하게 개선되었다. 그리고, 산화막 계면에서의 계면 전하 밀도는 게이트의 응력 완화에 따라서 개선되었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.539-542
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• 2001

In SiC semiconductor device processing, it needs high temperature anneal for activation of ion implanted dopants. The macrosteps, 7~8nm in height, are formed on the surface of SiC substrates during activation anneal. We have investigated the effect of thermally-grown SiO$_2$layer on the suppression of macrostep formation during high temperature anneal. The cap oxide layer was found to be efficient for suppression of macrostep formation even though the annealing temperature is as high as the melting point of SiO$_2$. The thin cap oxide layer (10nm) was evaporated during anneal then the macrosteps were formed on SiC substrate. On the other hand the thicker cap oxide layer (50nm) remains until the anneal process ends. In that case, the surface was smoother and the macrosteps were rarely formed. The thermally-grown oxide layer is found to be a good material for the suppression of macrostep formation because of its feasibility of growing and processing. Moreover, we can choose a proper oxide thickness considering the evaporate rate of SiO$_2$at the given temperature.

• Transactions on Electrical and Electronic Materials
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• 제1권4호
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• pp.1-6
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• 2000

The mechanical strength of silicon carbide dose nor permit the use of diffusion as a means to achieve selective doping as required by most electronic devices. While epitaxial layers may be doped during growth, ion implantation is needed to define such regions as drain and source wells, junction isolation regions, and so on. Ion activation without an annealing cap results in serious crystal damage as these activation processes must be carried out at temperatures on the order of 1600$^{\circ}C$. Ion implanted silicon carbide that is annealed in either a vacuum or argon environment usually results in a surface morphology that is highly irregular due to the out diffusion of Si atoms. We have developed and report a successful process of using silicon overpressure, provided by silane in a CAD reactor during the anneal, to prevent the destruction of the silicon carbide surface, This process has proved to be robust and has resulted in ion activation at a annealing temperature of 1600$^{\circ}C$ without degradation of the crystal surface as determined by AFM and RBS. In addition XPS was used to look at the surface and near surface chemical states for annealing temperatures of up to 1700$^{\circ}C$. The surface and near surface regions to approximately 6 nm in depth was observed to contain no free silicon or other impurities thus indicating that the process developed results in an atomically clean SiC surface and near surface region within the detection limits of the instrument(${\pm}$1 at %).

• Advances in nano research
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• 제2권4호
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• pp.179-186
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• 2014

Indium-nitrogen co-doped zinc oxide thin films (INZO) were prepared on glass substrates in the atmosphere by ultrasonic spray pyrolysis. The aqueous solution of zinc acetate, ammonium acetate and different indium sources: indium (III) chloride and indium (III) nitrate were used as the precursors. After film deposition, different anneal temperature treatment as 350, 450, $550^{\circ}C$ were applied. Electrical properties as concentration and mobility were characterized by Hall measurement. The surface morphology and crystalline quality were characterized by SEM and XRD. With the activation energy analysis for both films, the concentration variation of the films at different heat treatment temperature was realized. Donors correspond to zinc related states dominate the conduction mechanism for these INZO films after $550^{\circ}C$ high temperature heat treatment process.

• Transactions on Electrical and Electronic Materials
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• 제1권2호
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• pp.7-11
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• 2000

a-Si:H and poly-Si TFT(thin film transistor) characteristics were investigated using an inverted staggered type TFT. The TFT an as-grown a-Si:H exhibited a low field effect mobility, transconductance, and high gate threshold voltage. The poly-Si films were achieved by using an isothermal and RTA treatment for glow discharge deposited a-Si:H films. The a-Si:H films were cystallized at the various temperature from 600$^{\circ}C$ to 1000$^{\circ}C$. As anneal temperature was elevated, the TFT exhibited increased g$\sub$m/ and reduced V$\sub$ds/. V$\sub$T/. The poly-Si grain boundary passivation with grain boundary trap types and activation energies as a function of anneal temperature. The poly-si TFT showed an improved I$\sub$nm//I$\sub$off/ ratio of 10$\^$6/, reduced gate threshold voltage, and increased field effect mobility by three orders.

• 대한전자공학회논문지SD
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• 제41권5호
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• pp.37-42
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• 2004

본 논문에서는 선비정질화, 저에너지 이온 주입, 이중 열처리 공정을 이용하여 p/sup ＋/-n 박막 접합을 형성하였다. Ge 이온을 이용하여 결정 Si 기판을 선비정질화하였다. 선비정질화된 시편과 결정 기판에 p-형 불순물인 BF₂이온을 주입하여 접합을 형성하였다. 열처리는 급속 열처리 (RTA : rapid thermal anneal) 방법과 850℃의 노 열처리 (FA : furnace anneal) 방법을 병행하였다. 두 단계의 이중 열처리 방법으로 네 가지 조건을 사용하였는데, 이는 RTA(750℃/10초)＋Ft, FA＋RTA(750℃/10초), RTA(1000℃/10초)＋F4 FA＋RTA(1000℃/10초)이다. Ge 선비정질화를 통하여 시편의 접합 깊이를 감소시킬 수 있었다. RTA 온도가 1000℃인 경우에는 RTA보다는 FA를 먼저 수행하는 것이 접합 깊이(x/sub j/), 면저항(R/sub s/), R/sub s/ x/sub j/, 누설 전류 등의 모든 면에서 유리함을 알 수 있었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 하계학술대회 논문집 C
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• pp.1630-1632
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• 1997

We have investigated activation phenomena of implanted ions on silicon wafers using microwave(2.45GHz). It is found that the higher concentration of impurities makes the better activation effects by microwave annealing. We have exposed poly-Si TFTs by microwave in order to anneal and improved the device performance. Microwave activates source/drain ions and lowers the contact resistance so that the current of the poly-Si TFTs increases. In addition, the leakage current of hydrogen passivated poly-Si TFTs is decreased after microwave annealing, due to the diffusion of hydrogen ions and curing the defects in the poly-Si active channel.

• 대한전자공학회논문지
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• 제20권5호
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• pp.50-55
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• 1983

본 논문에서는 여러 가지 이온 도우스와 열처리 온도에 대해서 hall-effect/sheet resistivity 측정방법을 이용하여 실리콘을 주입한 크롬이 도핑된 GaAs의 전기적 성질에 관한 연구를 하였다. 시료는 상온에서 이온을 주입하였으며 실리콘 나이트라이드 캘핑을 하여 15권동안 수소수국기에서 열처리하였다. 연구된 모든 도우스에서 n형 층이 형성되었으며 최적 열처리 온도는 850℃이었다. 크롬이 도핑된 GaAs기판에 대해 최대 전기적 활성화 효률은 89%이었다. 캐리어 농도와 이동도의 depth profile은 이온 도우스와 열처 이에 매우 의존적이다. 800노의 열처리 후에도 이온 주입에 의해 생긴 손상이 일부 존재하고 있었으며 900℃ 열처리에서는 주입된 실리콘 이온의 약부확산과 외류확산이 있었다.

• 한국재료학회지
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• 제9권3호
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• pp.327-332
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• 1999

중성자에 조사 $(fluence: 2.3\times10^{19}ncm^{-2}, 553 K, E\geq1.0 MeV)$된 Mn-Mo-Ni 저 합금강 모재의 열처리 회복 거동을 조사하기 위하여 등시소둔과 등온소둔을 수행하여 회복 활성화에너지, 회복 반응차수 그리고 회복 반응률상수를 결정하였다. 열처리 후 회복은 비커스 미세 고온경도기로 측정하였고 실험결과를 이용, 열처리 회복단계, 회복결함들의 거동 및 회복 kinetics을 분석하였다. 실험결과 2단계의 회복구간(stage I : 703-753K, stage II : 813K-873K)이 나타났으며 각 단계의 회복활성화 에너지는 2.50 eV(1단계) 및 2.93 eV(2단계)이었다. 조사재와 비조사재의 등시소둔 곡선의 비교를 통하여 813K에서 RAH(radiation anneal hardening) 피크를 확인할 수 있었다. 743K 및 833K에서 수행한 등온소둔 결과, 회복의 60%가 모두 120분 이내에 일어나는 것으로 관찰되었다. 회복 반응차수는 두 회복구간에서 모두 2로 나타났으며 회복 반응율상수는 $3.4\times10^{-4}min^{-1}$(1단계)과 $7.1\times10^{-4}min^{-1}$(2단계) 이었다. 이상의 결과와 기 발표된 자료들을 함께 분석한 결과, 본 재료의 회복은 오랜 중성자조사로 형성된 점결함 집합체들이 열처리에 의한 분해와 Fe 기지에 격자간 원자로 존재하던 self-interstitial들과 vacancy들의 재결합에 의해 일어나는 것으로 해석된다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.109-109
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• 2010

$Er^{3+}$ ion shows a stable and efficient luminescence at 1.54mm due to its $^4I_{13/2}\;{\rightarrow}\;^4I_{15/2}$ intra-4f transition. As this corresponds to the low-loss window of silica-based optical fibers, Er-based light sources have become a mainstay of the long-distance telecom. In most telecom applications, $Er^{3+}$ ions are excited via resonant optical pumping. However, if nanocluster-Si (nc-Si) are co-doped with $Er^{3+}$, $Er^{3+}$ can be excited via energy transfer from excited electrical carriers in the nc-Si as well. This combines the broad, strong absorption band of nc-Si with narrow, stable emission spectra of $Er^{3+}$ to allow top-pumping with off-resonant, low-cost broadband light sources as well as electrical pumping. A widely used method to achieve nc-Si sensitization of $Er^{3+}$ is high-temperature annealing of Er-doped, non-stoichiometric amorphous thin film with excess Si (e.g.,silicon-rich silicon oxide(SRSO)) to precipitate nc-Si and optically activate $Er^{3+}$ at the same time. Unfortunately, such precipitation and growth of nc-Si into Er-doped oxide matrix can lead to $Er^{3+}$ clustering away from nc-Si at anneal temperatures much lower than ${\sim}1000^{\circ}C$ that is necessary for full optical activation of $Er^{3+}$ in $SiO_2$. Recently, silicon-rich silicon nitride (SRSN) was reported to be a promising alternative to SRSO that can overcome this problem of Er clustering. But as nc-Si formation and optical activation $Er^{3+}$ remain linked in Er-doped SRSN, it is not clear which mechanism is responsible for the observed improvement. In this paper, we report on investigating the effect of separating the nc-Si formation and $Er^{3+}$ activation by using hetero-multilayers that consist of nm-thin SRSO or SRSN sensitizing layers with Er-doped $SiO_2$ or $Si_3N_4$ luminescing layers.