• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2004년도 ICCAS
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• pp.741-746
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• 2004

We propose a new technique to the design and real-time implementation of an adaptive controller for robotic manipulator based on digital signal processors in this paper. The Texas Instruments DSPs(TMS320C80) chips are used in implementing real-time adaptive control algorithms to provide enhanced motion control performance for dual-arm robotic manipulators. In the proposed scheme, adaptation laws are derived from model reference adaptive control principle based on the improved direct Lyapunov method. The proposed adaptive controller consists of an adaptive feed-forward and feedback controller and time-varying auxiliary controller elements. The proposed control scheme is simple in structure, fast in computation, and suitable for real-time control. Moreover, this scheme does not require any accurate dynamic modeling, nor values of manipulator parameters and payload. Performance of the proposed adaptive controller is illustrated by simulation and experimental results for a dual arm robot consisting of two 4-d.o.f. robots at the joint space and cartesian space.

• ETRI Journal
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• 제30권1호
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• pp.113-128
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• 2008

Turbo codes are extensively used in current communications standards and have a promising outlook for future generations. The advantages of software defined radio, especially dynamic reconfiguration, make it very attractive in this multi-standard scenario. However, the complex and power consuming implementation of the maximum a posteriori (MAP) algorithm, employed by turbo decoders, sets hurdles to this goal. This work introduces an ASIP architecture for the MAP algorithm, based on a dual-clustered VLIW processor. It displays the good performance of application specific designs along with the versatility of processors, which makes it compliant with leading edge standards. The machine deals with multi-operand instructions in an innovative way, the fetching and assertion of data is serialized and the addressing is automatized and transparent for the programmer. The performance-area trade-off of the proposed architecture achieves a throughput of 8 cycles per symbol with very low power dissipation.

• Journal of Computing Science and Engineering
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• 제6권4호
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• pp.267-278
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• 2012

The state-of-the-art techniques in multicore timing analysis are limited to analyze multicores with shared instruction caches only. This paper proposes a uniform framework to analyze the worst-case performance for both shared instruction caches and data caches in a multicore platform. Our approach is based on a new concept called address flow graph, which can be used to model both instruction and data accesses for timing analysis. Our experiments, as a proof-of-concept study, indicate that the proposed approach can accurately compute the worst-case performance for real-time threads running on a dual-core processor with a shared L2 cache (either to store instructions or data).

• 전력전자학회논문지
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• 제9권1호
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• pp.50-57
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• 2004

일반적으로 두 대의 전동기를 독립적으로 동시에 구동하려면 2개의 독립적인 제어용 프로세서를 사용해 각각의 전력회로를 구동해야 한다. 본 논문에서는 CAN 네트워크를 이용해 한 개의 제어기만으로 두 대의 인버터 전력회로를 동시에 제어할 수 있는 단일 프로세서에 의한 복수 인버터 제어기법을 제안했다. 이 시스템은 두 대의 전동기를 한 개의 프로세서를 사용해 제어하기 때문에 두 대의 전동기를 연동하여 운전할 경우에도 별도의 인터페이스 장치나 새로운 프로세서의 추가 없이 소프트웨어적으로 간단히 구현할 수 있다. 제안된 시스템을 구현하고 실험을 통해 그 타당성을 입증해 보였다.

• 전자공학회논문지C
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• 제34C권6호
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• pp.44-50
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• 1997

This paper describes the design and test of an on-line non-invasive network performance monitor (hardware portion) for the SPAX parallel computer. The SPAX parallel computer supports up to 256 intel P6 processors with 4 P6 processors constituting a processign node. The nodes are interconnected with a dual two-level crossbar network calle dXcent-net. Since the performance of the SPAX parallel computer is highly dependent on the proper and efficient operation of the network, an on-line non-invasive network performance monitor (with hardware components) has been developed to aid in the monitoring and tunign of the Xcent-net. Successful testing of a prototype node monitor board and PC interface system shows that our monitor design provides a low-cost practical solution to this problem.

• Journal of Computing Science and Engineering
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• 제6권1호
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• pp.12-25
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• 2012

For real-time systems it is important to obtain the accurate worst-case execution time (WCET). Furthermore, how to improve the WCET of applications that run on multicore processors is both significant and challenging as the WCET can be largely affected by the possible inter-core interferences in shared resources such as the shared L2 cache. In order to solve this problem, we propose an innovative approach that adopts a code positioning method to reduce the inter-core L2 cache interferences between the different real-time threads that adaptively run in a multi-core processor by using different strategies. The worst-case-oriented strategy is designed to decrease the worst-case WCET among these threads to as low as possible. The other two strategies aim at reducing the WCET of each thread to almost equal percentage or amount. Our experiments indicate that the proposed multicore-aware code positioning approaches, not only improve the worst-case performance of the real-time threads but also make good tradeoffs between efficiency and fairness for threads that run on multicore platforms.

• 한국공작기계학회논문집
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• 제13권1호
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• pp.35-47
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• 2004

In this paper presents a new approach to the design and real-time implementation of fuzzy control system based-on digital signal processors(DSP:IMS320C80) in order to improve the precision and robustness for system of industrial robot(Dual-Arm with 8 joint Robot). The need to meet demanding control requirement in increasingly complex dynamical control systems under significant uncertainties, leads toward design of intelligent manipulation robots. The IMS320C80 is used in implementing real time fuzzy control to provide an enhanced motion control for robot manipulators. In this paper, a Self-Organizing Fuzzy Controller(SOFC) for the industrial robot manipulator with a actuator located at the base is studied. A fuzzy logic composed of linguistic conditional statements is employed by defining the relations of input-output variables of the controller. In the synthesis of a FLC(Fuzzy Logic Controller), one of the most difficult problems is the determination of linguistic control rules from the human operators. To overcome this difficult SOFC is proposed for a hierarchical control structure consisting of basic and high levels that modify control rules. The proposed SOFC scheme is simple in structure, Int in computation, and suitable for implementation of real-time control. Performance of the SOFC is illustrated by simulation and experimental results for a Dual-Arm robot with eight joints.

• Journal of information and communication convergence engineering
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• 제6권3호
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• pp.285-288
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• 2008

Most of multimedia processors for 2D/3D graphics acceleration use a lot of integer/floating point arithmetic units. We present a new architecture with an efficient ALU, built in a smaller chip size. It reduces instruction cycles significantly based on a foundation of multi-thread operation, variable length instruction words, dual phase operation, and phase instruction's coordination. We can decrease the number of instruction cycles up to 50%, and can achieve twice better performance.

• 정보처리학회논문지A
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• 제11A권3호
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• pp.199-206
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• 2004

다중 프로세서 시스템에서 여러 개의 프로그램이 동시에 수행될 경우의 프로그램 수행 성능은 각 프로세스를 어떠한 물리적 위치의 프로세서에 할당하여 수행하는가에 따라 다르게 나타난다. 일반적으로 시공간적으로 인접한 프로세서에 동일 프로그램의 프로세서를 할당할 경우 프로세스간 통신비용이 절감되므로 가장 효율적인 결과를 얻을 수 있다. 그러나 프로세스를 할당하는 운영체제는 이와 같은 친화성을 고려하기 위하여 부가적인 처리를 필요로 하며, 실제 수행시 각 프로그램은 독립적으로 수행되므로, 여러 프로그램으로부터 발생한 프로세스를 할당하는 방법은 많은 계산을 필요로 한다. 이중 링 구조의 CC-NUMA 시스템의 경우 특히 다수의 공유 메모리 접근에 의한 많은 트랜잭션이 발생하며, 연결망 부하의 불균등에 따른 병목 현상을 나타내므로, 프로세스의 할당 정책에 따라서 큰 성능 차이를 나타내게 된다. 본 논문은 규일한 연결망 부하특성을 나타내며, 프로세스 할당 정책을 필요로 하지 않는 CC-NUMA 시스템을 제시한다. 논문에서 제시하는 구조는 이중 링 구조와 동일한 연결망 비용을 나타내며, 건너뜀 연결을 이용한 균등한 부하 분배를 수행함으로써 프로세스 할당 정책의 유무와 무관한 성능을 보이다. 프로그램 구동 시뮬레이션을 통한 검증 결과 시스템은 이중 링 구조의 CC-NUMA 시스템에 비하여 1.5배의 성능 개선을 나타냈다.

• 대한전자공학회논문지
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• 제20권6호
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• pp.62-68
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• 1983

본 논문에서는, 처리 능력이 다른 두 개의 프로세서에 태스크를 최적으로 할당하기 위해, 동적인 재배치를 고려할 수 있는 의사 쌍대 그래프 모델을 제안한다. 전체 처리 비용을 최소화하기 위하여 태스크를 구성하고 있는 모델들을 두 프로세서에 최적 할당하는데, 이 그래프강에 복잡도가 0(n2)인 최단 경로 결정 알고리즘을 적용하여 해결할 수 있음을 보였다.