• Journal of the Institute of Electronics and Information Engineers
• /
• v.54 no.6
• /
• pp.93-99
• /
• 2017

In this research the TOF (time of flight) of ultrasonic signal is measured using Xilinx's Zynq SoC (system on chip). The TOF is calculated from the difference between periods during which RF (radio frequency) and ultrasonic signals come across a distance, and then travelling distance is obtained by multiplying the TOF by the ultrasonic speed in the air. For this purpose, a ultrasonic pulse is generated from a Zynq's internal ADC, a FIR (finite impulse response) filter, and a Kalman filter. And a RF reference pulse is generated from a RF interface. Based on baremetal multiprocessing, the Kalman filter and the RF interface are c-programmed on Zynq's dual processor cores, with other components fabricated on Zynq's FPGA. With this HW/SW co-design, both lower resource utilization and much smaller designing period were obtained than the HW design. As a design tool, Vivado IDE(integrated design environment) is used to design the whole signal processing system in hierarchical block diagrams.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.66 no.8
• /
• pp.1250-1256
• /
• 2017

In this research, a high-performance ultrasonic positioning system is proposed to track the positions of an indoor mobile object. Composed of an ultrasonic sender (mobile object) and a receiver (anchor), the system employs three ultrasonic time-off-flights (TOFs) and trilateration to estimate the positions of the object with an accuracy of sub-centimeter. On the other hand, because ultrasonic waves are interfered by temperature, wind and various obstacles obstructing the propagation while propagating in air, ultrasonic pulse debounce technique and Kalman filter were applied to TOF and position calculation, respectively, to compensate for the interference and to obtain more accurate moving object position. To perform tasks in real time, ultrasonic signals are processed full-digitally with a Zynq SoC, and as a software design tool, Vivado IDE(integrated design environment) is used to design the whole signal processing system in hierarchical block diagrams. And, a hardware/software co-design is implemented, where the digital circuit portion is designed in the Zynq's fpga and the software portion is c-coded in the Zynq's processors by using the baremetal multiprocessing scheme in which the c-codes are distributed to dual-core processors, cpu0 and cpu1. To verify the usefulness of the proposed system, experiments were performed and the results were analyzed, and it was confirmed that the moving object could be tracked with accuracy of sub-cm.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.8
• /
• pp.148-155
• /
• 2014

In this research a signal processing system is designed for detecting the ultrasonic signal envelope using Xilinx's Zynq SoC(system on chip). As a design tool, Vivado IDE(integrated design environment) is used to hierarchically design the whole signal processing system. The proposed system consists of a Zynq-internal ADC, an FIR(finite impulse response) BPF(band pass filter), an absolute value calculator, an FIR LPF(lpw pass filter), and the Kalman filter. Under this configuration, two design schemes, HW design scheme with LPF as a final stage and HW/SW co-design scheme with a Kalman filter as a final stage, are compared in terms of the performance and efficiency. As a result, envelope detecting performances of the two schemes are proved to be almost same, but the HW/SW co-design is verified to be much more efficient than the HW design considering the much smaller time consumption during system design.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.8 no.1
• /
• pp.159-164
• /
• 2013

Recently the solution integrated of vision and motion controller which are important element in automatiomn system has been many developed. However typically such a solutions has a many case that integrated vision processing and motion control into network or organized two chip solution on one module. We implement one chip solution integrated into vision and motion controller using Zynq-7000 that is developed recently as extended processing platform. We also apply EtherCAT to motion control that is industrial Ethernet protocol which have compatibility for open standardization Ethernet in order to control of motion because EtherCAT has a secure to realtime control and can treat massive data.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2015.10a
• /
• pp.219-222
• /
• 2015

하드웨어 검증은 하드웨어 디자인 단계에서 필수 요소이다. 하드웨어 검증은 시뮬레이션 방식과 에뮬레이션 방식으로 나뉘며, 상대적으로 빠른 에뮬레이션 방식을 이용해 최종적으로 하드웨어를 검증한다. 하지만 에뮬레이션 방식 역시 실제 하드웨어의 동작과 비교하면 상당히 느린 편이다. 본 연구는 보다 빠른 에뮬레이션이 가능한 Xilinx의 하이브리드 에뮬레이션 디바이스 Zynq의 성능을 정량화하여 에뮬레이션 장비와 실제 하드웨어 장비의 성능을 비교 및 분석한다. Zynq의 비교 대상으로는 이와 유사한 하드웨어 구조 및 사양을 가진 상용 디바이스 Tegra3를 비교하였다. 실험 결과 Zynq는 Tegra3에 비해 벤치마크의 수행에 있어서 상대적으로 낮은 성능을 보였다. 하지만 Zynq는 에뮬레이션 환경인 것을 감안하면 병렬성이나 벤치마크 실행 속도 측면에서 기존의 에뮬레이션 환경보다 높은 성능을 보여 주었다.

• Journal of IKEEE
• /
• v.24 no.1
• /
• pp.186-193
• /
• 2020

In this paper, we propose a multi-threading system to support reconfigurable hardware accelerators on Zynq SoC. We implement high-performance JPEG decoder with reconfigurable 2D IDCT hardware accelerators to achieve maximum performance available on the platform. In this system, up to four reconfigurable hardware accelerators synchronized with SW threads can be dynamically reconfigured to provide adaptive computing capabilities according to the given image resolution and the compression ratio. JPEG decoding is operated using images with resolutions 480p, 720p, 1080p at the compression ratio of 7:1-109:1. We show that significant performance improvements are achieved as the image resolution or the compression ratio increase. For 1080p resolution, the performance improvement is up to 79.11 times with throughput speed of 99 fps at the compression ratio 17:1.

• Journal of IKEEE
• /
• v.23 no.3
• /
• pp.925-933
• /
• 2019

In this paper, we implement ZYNQ SoC-based post-processing system that utilizes partial reconfiguration to remove blocking artifacts generated by compression algorithm. Hardware implementation of the deblocking filter in a Field Programmable Gate Array (FPGA) provides high computational capability and can be partially reconfigured to process 1080p images in real time. Partially reconfigurable areas in FPGA can be utilized to use hardware more efficiently in highly resource-constrained embedded systems. Experimental results of the proposed system show improvement of visual quality both objectively and subjectively with 0.6dB higher PSNR after deblocking filtering process. The measured power consumption of the deblocking filter during run-time is 68.33mW.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.13 no.1
• /
• pp.17-24
• /
• 2018

Military camera equipment has a problem that observability is inferior due to various shaking factors. In this paper, we propose an image stabilization algorithm considering performance and execution time to solve this problem and implemented it in Zynq SoC. We stabilized both the simple shaking in the fixed observation position and the sudden shaking in the moving observation position. The feature of the input image is extracted by the Sobel edge algorithm, the subblock with the large edge data is selected, and the motion vector, which is the compensation reference, is calculated through template matching using the 3-step search algorithm of the region of interest. In addition, the proposed algorithm can distinguish the shaking caused by the simple shaking and the movement by using the Kalman filter, and the stabilized image can be obtained by minimizing the loss of image information. To demonstrate the effectiveness of the proposed algorithm, experiments on various images were performed. In comparison, PSNR is improved in the range of 2.6725~3.1629 (dB) and image loss is reduced from 41% to 15%. On the other hand, we implemented the hardware-software integrated design using HLS of Xilinx SDSoC tool and confirmed that it operates at 32 fps on the Zynq board, and realized SoC that operates with real-time processing.

• Journal of Internet Computing and Services
• /
• v.17 no.4
• /
• pp.11-17
• /
• 2016

In this paper, we proposed a multi-viewer system with multiple HD cameras based AVB(Audio Video Bridge) ethernet cable using IP networking, and FPGA(Xilinx Zynq 702) for bus safety systems. This AVB (IEEE802.1BA) system can be designed for the low latency based on FPGA, and transmit real-time with HD video and audio signals in a vehicle network. The proposed multi-viewer platform can multiplex H.264 video signals from 4 wide-angle HD cameras with existed ethernet 1Gbps. and 2-wire 100Mbps cables. The design of Zynq 702 based low latency to H.264 AVC CODEC was proposed for the minimization of time-delay in the HD video transmission of car area network, too. And the performance of PSNR(Peak Signal-to-noise-ratio) was analyzed with the reference model JM for encoding and decoding results in H.264 AVC CODEC. These PSNR values can be confirmed according the theoretical and HW result from the signal of H.264 AVC CODEC based on Zynq 702 the multi-viewer with multiple cameras. As a result, proposed AVB multi-viewer platform with multiple cameras can be used for the surveillance of audio and video around a bus for the safety due to the low latency of H.264 AVC CODEC design.

• Journal of Advanced Navigation Technology
• /
• v.19 no.5
• /
• pp.423-432
• /
• 2015

This paper shows that design, manufacture and the performance of FC-NIC (fibre channel network interface card) for network unit configuration which is based on one of the 5 main configuration items of the common functional module for IMA (integrated modular Avionics) architecture. Especially, FC-NIC uses zynq SoC (system on chip) for host load reductions. The host merely transmit FC destination address, source memory location and size information to the FC-NIC. After then the FC-NIC read the host memory via DMA (direct memory access). FC upper layer protocol and sequence process at local processor and programmable logic of FC-NIC zynq SoC. It enables to free from host load for external communication. The performance of FC-NIC shows average 5.47 us low end-to-end latency at 2.125 Gbps line speed. It represent that FC-NIC is one of good candidate network for IMA.