• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.10 s.113
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• pp.959-966
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• 2006

This paper proposes a new concept about dual band predistortion linear power amplifier(PD LPA) using diplexer for digital cellular ($f_o$=880 MHz) and IMT-2000($f_o$=2,140 MHz) base stations. The diplexer is composed of low pass filter having defected ground structure(BGS) microstrip line and high pass filter having high-Q lumped capacitors and distributed elements. The proposed predistorter adopts a reflection type intermodulation signal generator with 3 dB hybrid coupler for good reflection characteristic. for a forward link one carrier CDMA IS-95A 1FA and WCDMA 1FA signal, the proposed dual band PD LPA shows the adjacent channel leakage ratio(ACLR) improvement about 10 dB and 9.36 dB for digital cellular and IMT-2000 band, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.7
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• pp.713-721
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• 2004

This paper presents a high Performance LNA based on InGaP/GaAs HBT for 5.4㎓ WAM band applications. During the past days, InGaP/GaAs HBT has been being used for mainly high power amplifiers, but InCaP/GaAs is recognized as a suitable device for RF single chip. At this point, the research about a high performance LNA based on InGaP/GaAs HBT must be preceded, and in this paper, a excellent linearity and noise characteristics LNA based on InGaP/GaAs HBT is desisted and fabricated. The LNA is integrated in new of 0.9${\times}$0.9$\textrm{mm}^2$ single chip with high Q spiral inductors and MIM capacitors. The proposed LNA is biased at current point for optimum noise figure and gain characteristics, futhermore, excellent linearity is achieved. The proposed LNA shows 13㏈ gain, 2.1㏈ noise figure, and excellent linearity in terms of IIP3 of 5.5㏈m.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.8
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• pp.798-804
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• 2013

In this paper, conducted emission from the LDC(Low-Side DC/DC Converter) of a HEV/EV was analyzed using high-frequency circuit modeling in system-level approach. The conducted emission by PWM process(100 kHz; Switching Frequency) can cause RFI(Radio-Frequency Interference) problems in the AM/FM frequency range. In order to mitigate this conducted emission, a high-frequency equivalent circuit model is proposed by analyzing the fundamental circuits, parasitic components in their parts and connections and non-linear characteristics of MOSFETs, high-power capacitors, inverters, motors, high-power cables, and bus bars which are composed of the LDC. Using these circuit models, results of both simulation and measurement were compared and similarities between them were verified. We are looking forward that this approach can be effectively used in the EMC design of HEV/EV.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.5
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• pp.791-796
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• 2017

In this study, we investigated the influence of the fabrication process of stacked capacitors on the cell capacitance by using Load Lock (L/L) LPCVD system for dielectric thin film of DRAM capacitor. As a result, it was confirmed that the capacitance difference of about 3-4 fF is obtained by reducing the effective thickness of the oxide film by about $6{\AA}$ compared to the conventional non-L/L device. In addition, Cs was found to be about 3-6 fF lower than the calculated value, even though the measurement range of the thickness of the nitride film as an insulating film was in a normal management range. This is because the node poly FI CD is managed at the upper limit of the spec, resulting in a decrease in cell surface area, which indicates a Cs reduction of about 2fF. Therefore, it is necessary to control the thickness of insulating film and CD management within 10% of the spec center value in order to secure stable Cs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.146-153
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• 2008

In this paper, a integrated phase-locked loop(PLL) as a clock multiphase generator for a high speed serial link is designed. The designed PLL keeps the same bandwidth and damping factor by using programmable current mirror in the whole operation frequency range. Also, the close-loop transfer function and VCO's phase-noise transfer function of the designed PLL are obtained with circuit netlists. The self impedance on board-mounted chip is calculated according to sizes and positions of decoupling capacitors. Especially, the detailed self-impedance analysis is carried out between frequency ranges represented the maximum gain in the close-loop transfer function and the maximum gain in the VCO's phase noise transfer function. We shows PLL's jitter characteristics by decoupling capacitor's sizes and positions from this result. The designed PLL has the wide operating range of 0.4GHz to 2GHz in operating voltage of 1.8V and it is designed 0.18-um CMOS process. The reference clock is 100MHz and PLL power consumption is 17.28mW in 1.2GHz.

• Journal of Advanced Marine Engineering and Technology
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• v.41 no.1
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• pp.76-82
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• 2017

Since the introduction of electronically controlled engines and electric propulsion ships, the need for an uninterruptible power supply for emergency power supply devices that use batteries has gained importance. The bidirectional converter in such emergency power supply devices is a crucial component. This paper proposes, a topology for an improved DC-DC bidirectional converter that is characterized by a high voltage conversion ratio and low voltage stress of switches. To confirm the performance of the converter, a computer simulation was executed with PSIM software. The conversion ratio of the proposed converter was found to be four times higher than the conventional boost converter in step-up mode and one-fourth that of the conventional buck converter in step-down mode, and the voltage stress of the switches was one-fourth of the high-side voltage. Moreover, the proposed converter was confirmed to be able to distribute equal currents between two interleaved modules without using any extra current-sharing control method because of the charge balance of its blocking capacitors.

• Journal of the Korean Vacuum Society
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• v.10 no.2
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• pp.189-193
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• 2001

We have characterized physical and electrical properties of W-TiN stacked gate electrode structure with TiN as a diffusion barrier of fluorine. As the $N_2/Ar$ gas ratio increased during sputter deposition, TiN thin films became N-rich, and the resistivity of the films increased. However, the resistivity of W-TiN stacked gate reduced as a result of the crystallization of tungsten with the increase of $N_2/Ar$ gas ratio. On the other hand, tungsten in W-TiN stacked gate structure have the (100)-oriented crystalline structure although TiN films were subjected to annealing at high temperature (600~$800^{\circ}C$). Leakage currents of W-TiN gate MOS capacitors were less than $10^{-7}\textrm{/Acm}^2$ and also were lowered by the order of 2 compared with those of pure W gate electrode.

• Journal of the Korean Vacuum Society
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• v.5 no.4
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• pp.333-340
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• 1996

The properties of TiN as a barrier against Cu diffusion ere studied by sheet resistance measurement, X-ray diffraction, scanning electron microscopy, Auger electron spectroscopy, and capacitance-voltage(C-V) measurement. The sensitivities of the various methods were compared. Specimens with Cu/TiN/Ti/SiO2/Si structure were prepared by various deposition techniques and annealed at various temperatures ranging from $500^{\circ}C$ to $800^{\circ}C$ in 10%H2/90%Ar ambient for hours. As the effectiveness of the barrier property of TiN against Cu diffusion was vanished, the irregular-shaped sports were observed and outdiffused Si were detected on the surface of the Cu thin film. The C-V characteristics of the MOS capacitors varied drastically with annealing temperatures. In C-V measurement, the inversion capacitance decreased at annealing temperature range from $500^{\circ}C$ to $700^{\circ}C$ and increased remarkably at $800^{\circ}C$. These variations may be due to the Cu diffusion through TiN into $SiO_2$ and Si.

• Korean Journal of Materials Research
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• v.10 no.5
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• pp.360-363
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• 2000

Deformation in the hysteresis loop of $Pb(Zr,Ti)O_3$ (PZT) thin films with various Zr/Ti ratios has been studied by varying the top electrode preparation method and the annealing temperature. Pt/PZT/Pt capacitors was found to be positively poled due to dc plasma potential generated during reactive ion etch (RIE) of Rt. Internal field is formed by space charges trapped at domain boundaries. Aging phenomenon such as constriction in the middle of the hysteresis loop was observed in the PZT film with top electrode deposited by sputtering. Top electrode annealing restores the hysteresis loop by removing the space charges. As Zr/Ti ratio decrease, voltage shift increases and an-nealing temperature at which internal field disappears also increases.

• Korean Journal of Materials Research
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• v.4 no.4
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• pp.453-458
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• 1994

$(Ba_{0.5}Sr_{0.5)/TiO_3$(BST) thin films were prepared for the application of 256 Mb DRAM by RF magnetron sputtering. The crystallinity of BST thin films increased with increasing deposition tempera lure. The composition of thin films was $(Ba_{0.48}Sr_{0.48)/TiO_{2.93}$ Pt/Ti barrier layer suppressed the diffusion of Si into BST layer. The films showed a dielectric constant of 320 and a dissipation factor of 0.022 at 100 kHz. the change of capacitance of the films with applied voltage was small, showing paraelectric property. The charge storage density and leakage current density were 40fC/$\mu \textrm{m}^{2}$ and 0.8$\mu A/\textrm{cm}^2$, respectively at a field of 0.15 MV/cm. The BST films obtained by RF magnetron sputtering appeared to be potential thin film capacitors for 256 Mb DRAM application.