• 한국전자현미경학회:학술대회논문집
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• 1997.05a
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• pp.62-64
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• 1997

• Journal of the Korean institute of surface engineering
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• v.35 no.5
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• pp.289-294
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• 2002

ZnTe films have been grown on (100) GaAs substrate with two representative problems. The one is lattice mismatch, the other is thermal expansion coefficients mismatch of ZnTe /GaAs. It claims here, the relationship of film thickness and defects distribution with (100) ZnTe/GaAs using hot wall epitaxy (HWE) growth was investigated by transmission electron microscopy (TEM). It analyzed on the two-sort side using TEM with cross-sectional transmission electron microscopy (XTEM) and high-resolution electron microscopy (HREM). Investigation into the nature and behavior of dislocations with dependence-thickness in (100) ZnTe/ (100) GaAs hetero-structures grown by transmission electron microscopy (TEM). This defects range from interface to 0.7 $\mu\textrm{m}$ was high density, due to the large lattice mismatch and thermal expansion coefficients. The defects of low density was range 0.7$\mu\textrm{m}$~1.8$\mu\textrm{m}$. In the thicker range than 1.8$\mu\textrm{m}$ was measured hardly defects.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.331-334
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• 1998

p형 실리콘 기판위에 100.angs.의 초기 산화막을 성장시킨 후 붕소(B)와 인(P)을 1MeV 이온주입 에너지로 4.dec. tilting하여 붕소의 도즈량은 1*10/녀ㅔ 13/[cm/sup -2/]까지, 인은 1*10/sup 13/[cm/sup -2]로부터 1*10/sup 14/[cm/sup -2/] 까지 변화시키며 이온 주입하였다. 이온주입 후 RTA 로서 열처리 하였으며, 열처리 시간은 10초에서 40초까지,열처리 온도를 1000.deg.C에서 1100.deg.C까지 변화하였다. 이후 기파낸의 불순물의 프로파일 및 미세 결함의 분포를 분석하기 위하여, SIMS, SRP, XTEM 분석을 실시하였고, 이를 monte-carlo 모ㅓ델로서 시뮬레이션하여 비교하였다. SIMS 분석 결과 열처리 온도와 시간이 증가할수록 접합깊이가 증가하였고, 프로파일이 넓어짐을 볼수 있다. SRP 측정에서 붕소는 주해거리 (Rp)값은 1.8.mu.m~1.9.mu.m, 인의 경우는 1.1.mu.m~1.2.mu.m의 주행거리 (Rp) 값이 나타났다. XTEM 분석결과 붕소의 경우 열처리에 전후에도 결함을 볼수 없었고, 인의 경우 열처리 이후에 실리콘 결정내부에 있던 산소(O)와 인(P)우너자의 pinning효과에 의해 전위다이폴을 형성하여 표면근처로 성장함을 볼수 있었다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.8
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• pp.42-48
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• 1993

Ar ions were implanted at 1 MeV into (100)Cz Si wafers with dose of 1 * 10$^{15}$ ions/cm$^{2}$. Damage induced by high energy implantation and its annealing behavior during rapid thermal annealing for 10sec at temperatures from 550 to 1100${\circ}C$ were investigated by crosssection transmission electron microscopy study. It can be clearly seen from the observation that the SPE(Solid Phase Epitaxy) regrowth of the buried amorphous layer induced by ion implantation proceeds from both upper and lower amorphous/crystalline (a/c) interfaces, and the activation energy for SPE from interfaces were both 1.43eV. Misfit dislocation where two interfaces met was formed and it coalesced into the hair pin dislocation in the upper regrown region. At the higher temperature after annealing out of the misfit dislocation, hair pin dislocations showed considerable drop in its bandwidth. However, they were not disappeared even at the temperature 1100${\circ}C$ with the end of range dislocation loops which were formed at the original lower a/c interface.

• Proceedings of the Korean Ceranic Society Conference
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• 1986.12a
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• pp.287-304
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• 1986

High quality monocrystalline $\beta$-SiC thin films were grown via two-step process of conversion of the Si(100) surface by reaction with $C_2H_4$ and the subsequent chemical vapor deposition (CVD) at $1360^{\circ}C$ and 1 atm total pressure. Four dopants, B and Al and p-type, and N and P for n-type, were also incorporated into monocrystalline $\beta$-SiC thin films during the CVD growth process. IR and Raman spectroscopies were used to evaluate the quality of the undoped $\beta$-SiC thin films and to investigate the effects of dopants on the structure of the doped $\beta$-SiC thin films. The changes in the shape of IR and Raman spectra of the doped thin films due to dopants were observed. But the XTEM micrographs except for the B-doped and annealed films showed the same density and distribution of stacking faults and dislocations as was seen in the undoped samples, The IR and Raman spectra of the B-doped and annealed films showed the broad and weak bands and one extra peak at the 850 $cm^{-1}$ respectively. The SAD pattern and XTEM micrograph of the B-doped and annealed film provided the evidence for twinning.

• Journal of the Korean institute of surface engineering
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• v.34 no.5
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• pp.475-480
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• 2001

Diffusion of Cu into the low-k para-xylene based plasma polymer (pXPP) thin films deposited by plasma-enhanced chemical vapor deposition using the para-xylene precursor was comparatively measured using various methods. Cu layer was deposited on the surfaces of pXPPs treated by $N_2$ plasma generated in a magnetically enhanced inductively coupled plasma reactor. Diffusion characteristics of Cu into pXPPs were measured using Rutherford backscattering spectroscopy (RBS), secondary ion mass spectroscopy (SIMS), cross-sectional transmission electron microscopy (XTEM), and current-voltage (I-V) measurements for the vacuum-annealed Cu/pXPPs for 1 hour at $450^{\circ}C$ and were compared. The results showed a correlation between the I-V measurement and SIMS data are correlated and have a sensitivity enough to evaluate the dielectric properties but the RBS or XTEM measurements are not sufficient to conclude the electrical properties of low-k dielectrics with Cu in the film bulk. The additional results indicate that the pXPP layers are quite resistant to Cu diffusion at the annealing temperature of $450^{\circ}C$ compared to the other previously reported organic low-k materials.

• Journal of IKEEE
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• v.2 no.1 s.2
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• pp.101-107
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• 1998

This paper is studied micro-defect characteristics by phosphorus 1MeV ion implantation and Rs, SRP, SIMS, XTEM for the RTA process was measured and simulated. As the dose is higher, the Rs is lower. When the dose are $1{\times}10^{13}/cm^2,\;5{\times}10^{13}/cm^2,\;1{\times}10^{14}/cm^2$, the Rp are $1.15{\mu}m,\;1.15{\mu},\;1.10{\mu}m$ respectively. As the RTA time is longer, the maximum concentration position is deeper from the surface and the concentration is lower. Before the RTA was done, we didn't observe any defect. But after the RTA process was done, we could observe the RTA process changed the micro-defects into the secondary defects. The simulation using the buried layer and connecting layer structure was performed. As results, the connecting layer had more effect than the buried layer to latch-up immune. Trigger current was more $0.6mA/{\mu}m$ and trigger voltage was 6V at dose $1{\times}10^{14}/cm^2$ and the energy 500KeV of connecting layer Lower connecting layer dose, latch-up immune characteristics was better.

• Journal of the Korean Vacuum Society
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• v.1 no.3
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• pp.376-381
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• 1992

Tungsten silicide films were deposited on the highly phosphorus-doped poly Si/SiO2/Si substrates by Low Pressure Chemical Vapor Deposition. They were heat treated in different conditions. XTEM, SIMS and high frequency C-V analysis were conducted for characterization. It can be concluded that outdiffusion of phosphours impurity throught the silicide films lead to its depletion in the poly-Si gate region near the gate oxide, resulting in loss of capacitance and increase of effective gate oxide thickness.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.9 no.1
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• pp.39-42
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• 1999

Nitrogen-doped SiC(3C) (N-SiC(3C)) epliayers were grown on Si(111) substrate at $1250^{\circ}C$ using chemical vapor deposition (CVD) technique by pyrolyzing tetramethylsilane(TMS) in $H_{2}$ carrier gas. SiC(3C) layer was doped using $NH_{3}$ during the CVD growth to be n-type conduction. Physical properties of N-SiC(3C) were investigated by Fourier transform infrared (FTIR) spectroscopy, X-ray diffraction (XRD) patterns, Raman spectroscopy, cross-sectional transmission electron microscopy (XTEM), Hall measurement, and current-voltage(I-V) characteristcs of the N-SiC(3C)/Si(p) diode. N-SiC(3C) layers exhibited n-type conductivity. The n-type doping of SiC(3C) could be controlled by nitrogen dopant using $NH_{3}$ at low temperature.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.197-197
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• 1999

Gate oxide 의 두께 감소는 gate의 캐패시턴스를 증가시켜 트랜지스터의 속도를 빠르게 하며, 동시에 저전압 동작을 가능하게 하기 때문에 gate oxide 두께는 MOS 공정 세대가 진행되어감에 따라 계속 감소할 것이다. 이러한 얇은 산화막은 device design에 명시된 두께의 특성을 나타내야 한다. Gate oxide의 두께가 작아질수록 gate oxide와 crystalline silicon간의 계면효과가 박막의 두께의 결정에 심각한 영향을 주기 때문에 정확한 두께 계측이 어렵다. 이러한 영향과 계측방법에 따라서 두께 계측의 차이가 나타난다. XTEM은 사용한 parameter에, Ellipsometer는 refractive index에, MEIS(Medium) Energy Ion Scattering)은 에너지 분해능에, Capacitor-Voltage 측정은 depletion effect에 의해 영향을 받는다. 우리는 계면의 원자분해능 분석에 통상 사용되어온 High Resolution TEM을 이용하여 약 30~70$\AA$ SiO2층의 두께와 계면 구조에 대한 분석을 하여 이를 MEIS와 0.015nm의 고감도를 가진 SE(Spectroscopy Ellipsometer), C-V 측정 결과와 비교하여 가장 좋은 두께 계측 방법을 찾고자 한다.