• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2007.11a
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• pp.68-68
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• 2007

• Journal of Advanced Navigation Technology
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• v.13 no.5
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• pp.691-698
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• 2009

Chen et al. proposed a RFID authentication protocol for anti-counterfeiting and privacy protection. A feasible security mechanism for anti-counterfeiting and privacy protection was proposed using XOR and random number shifting operations to enhance RFID tag's security providing a low cost. However, their authentication protocol has some drawbacks and security problems because they did not consider the surrounding environments. We conduct analysis on the protocol and identify problematic areas for improvement of the research. We also provide enhanced authentication and update scheme based on the comment for efficient supply chain management. The proposed protocol was analyzed and compared with typical XOR based RFID authentication protocols and it was confirmed that our protocol has high safety and low communication cost.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.24-30
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• 2003

This study focuses on the arithmetical methodology and hardware implementation of low system-complexity A $B^2$＋C operator over GF(2$^{m}$ ) using the irreducible AOP of degree m. The proposed parallel-in parallel-out operator is composed of CS, PP, and MS modules, each can be established using the array structure of AND and XOR gates. The proposed multiplier is composed of (m＋1)$^2$ 2-input AND gates and (m＋1)(m＋2) 2-input XOR gates. And the minimum propagation delay is $T_{A}$ ＋(1＋$\ulcorner$lo $g_2$$^{m}$ $\lrcorner$) $T_{x}$ . Comparison result of the related A $B^2$＋C operators of GF(2$^{m}$ ) are shown by table, It reveals that our operator involve more lower circuit complexity and shorter propagation delay then the others. Moreover, the interconnections of the out operators is very simple, regular, and therefore well-suited for VLSI implementation.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10a
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• pp.658-660
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• 2003

경매 프로토콜의 우수성은 보안성, 효율성, 안정성의 측면에 있다. 기존에 제안된 경매 프로토콜은 보안을 강화함으로 인해 많은 계산량과 메시지 전승이 요구되어 높은 트래픽을 발생한다. 또한 경매의 규모가 커짐에 따라 Auctioneer의 부담이 가중된다. 본 논문에서는 다항함수의 특성과 개인 정보 분할을 통해 기존의 보안성을 유지하면서도 효율성을 높인 경매 프로토콜 PAP를 제안하고자 한다. 효율성을 높이기 위해 곱연산을 피하고 xor연산을 이용하여 계산량을 줄이고. 안전성을 높이기 위해 다항함수(Polynomial)의 기본 성질을 이용해서 Bidder들의 정보를 분할한다. 제안한 경매 프로토콜은 계산량을 줄이면서도 Bidder들의 정보는 보호된다.

• Proceedings of the KAIS Fall Conference
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• 2010.05a
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• pp.503-506
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• 2010

유비쿼터스 사회를 만들기 위한 핵심 기술인 RFID는 시간과 공간을 초월하여 우리에게 정보를 제공해 줄 것으로 기대되고 있지만, RFID 시스템이 가지고 있는 특성으로 인하여 프라이버시를 침해할 수 있다는 심각한 문제를 안고 있다. 이를 해결하기 위한 방법으로 다양한 연구가 진행되어 왔지만 기존의 연구들은 보안상 문제점과 태그 및 백 엔드 데이터베이스의 과도한 처리능력을 요구하고 있다. 그러나 본 논문에서 제안하는 프로토콜은 해쉬함수와 XOR연산, 키 교환을 이용하여 스푸핑이나, 재전송 공격으로부터 안전 하면서도, 백 엔드 데이터베이스 안에서의 비교연산 횟수를 줄일 수 있는 경량화된 프로토콜을 제안한다.

• Proceedings of the KAIS Fall Conference
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• 2010.05a
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• pp.491-494
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• 2010

유비쿼터스 사회를 만들기 위한 핵심 기술인 RFID는 시간과 공간을 초월하여 우리에게 정보를 제공해 줄 것으로 기대되고 있지만, RFID 시스템이 가지고 있는 특성으로 인하여 프라이버시를 침해할 수 있다는 심각한 문제를 안고 있다. 이를 해결하기 위한 방법으로 다양한 연구가 진행되어 왔지만 기존의 연구들은 보안상 문제점과 태그 및 백 엔드 데이터베이스의 과도한 처리능력을 요구하고 있다. 그러나 본 논문에서 제안하는 프로토콜은 해쉬함수와 XOR연산, 키 교환을 이용하여 스푸핑이나, 재전송 공격으로부터 안전 하면서도, 백 엔드 데이터베이스 안에서의 비교연산 횟수를 줄일 수 있는 경량화된 프로토콜을 제안한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.84-95
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• 2006

In H/W implementation for the finite field the use of normal basis has several advantages, especially, the optimal normal basis is the most efficient to H/W implementation in $GF(2^m)$. In this paper, we propose a new, simpler, parallel multiplier over $GF(2^m)$ having a Gaussian normal basis of type k, which performs multiplication over $GF(2^m)$ in the extension field $GF(2^{mk})$ containing a type-I optimal normal basis. For k=2,4,6 the time and area complexity of the proposed multiplier is the same as tha of the best known Reyhani-Masoleh and Hasan multiplier.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.1-10
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• 2004

A cellular array parallel multiplier with parallel-inputs and parallel-outputs for performing the multiplication of two polynomials in the finite fields GF$(2^m)$ is presented in this paper. The presented cellular way parallel multiplier consists of three operation parts: the multiplicative operation part (MULOP), the irreducible polynomial operation part (IPOP), and the modular operation part (MODOP). The MULOP and the MODOP are composed if the basic cells which are designed with AND Bates and XOR Bates. The IPOP is constructed by XOR gates and D flip-flops. This multiplier is simulated by clock period l${\mu}\textrm{s}$ using PSpice. The proposed multiplier is designed by 24 AND gates, 32 XOR gates and 4 D flip-flops when degree m is 4. In case of using AOP irreducible polynomial, this multiplier requires 24 AND gates and XOR fates respectively. and not use D flip-flop. The operating time of MULOP in the presented multiplier requires one unit time(clock time), and the operating time of MODOP using IPOP requires m unit times(clock times). Therefore total operating time is m+1 unit times(clock times). The cellular array parallel multiplier is simple and regular for the wire routing and have the properties of concurrency and modularity. Also, it is expansible for the multiplication of two polynomials in the finite fields with very large m.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.26 no.6
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• pp.1443-1454
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• 2016

Balanced encoding method that implement Dual-rail logic style based on hardware technique to software is efficient countermeasure against side-channel analysis without additional memory. Since balanced encoding keep Hamming weight and/or Hamming distance of intermediate values constantly, using this method can be effective as countermeasure against side channel analysis due to elimination of intermediate values having HW and/or HD relating to secret key. However, former studies were presented for Constant XOR operation, which can only be applied to crypto algorithm that can be constructed XOR operation, such as PRINCE. Therefore, our first proposal of new Constant ADD, Shift operations can be applied to various symmetric crypto algorithms based on ARX. Moreover, we did not used look-up table to obtain efficiency in memory usage. Also, we confirmed security of proposed Constant operations with Mutual Information Analysis.

• Journal of IKEEE
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• v.23 no.3
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• pp.878-882
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• 2019

XOR(exclusive-OR)-XNOR(exclusive NOR) circuit is a basic component of 4-2 compressor for high performance arithmetic operation. In this paper we propose an energy efficient XOR-XNOR circuit. The proposed circuit is reduced the internal parasitic capacitance in critical path and implemented with 8 transistors. The circuit produces a perfect output signals for all input combinations. Compared with the previous circuits, the proposed circuit has a 14.5% reduction in propagation delay time and a 1.7% increase in power consumption. Therefore, the proposed XOR-XNOR is reduced power-delay- product (PDP) by 13.1% and energy-delay-product (EDP) by 26.0%. The proposed circuits are implemented with standard CMOS 0.18um technology and verified through SPICE simulation with 1.8V supply voltage.