• ETRI Journal
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• 제37권1호
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• pp.157-164
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• 2015

As GPU power consumption in smartphones increases with more advanced graphic performance, it becomes essential to estimate GPU power consumption accurately. The conventional GPU power model assumes, simply, that a GPU consumes constant power when turned on; however, this is no longer true for recent smartphone GPUs. In this paper, we propose an accurate GPU power model for smartphones, considering newly adopted dynamic voltage and frequency scaling. For the proposed GPU power model, our evaluation results show that the error rate for system power estimation is as low as 2.9%, on average, and 4.6% in the worst case.

• Journal of Computing Science and Engineering
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• 제8권4호
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• pp.215-227
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• 2014

In modern computer architectures, caches are widely used to shorten the gap between processor speed and memory access time. However, caches are time-unpredictable, and thus can significantly increase the complexity of worst-case execution time (WCET) analysis, which is crucial for real-time systems. This paper proposes a time-predictable two-level scratchpad-based architecture and an ILP-based static memory objects assignment algorithm to support real-time computing. Moreover, to exploit the load/store latencies that are known statically in this architecture, we study a Scratch-pad Sensitive Scheduling method to further improve the performance. Our experimental results indicate that the performance and energy consumption of the two-level scratchpad-based architecture are superior to the similar cache based architecture for most of the benchmarks we studied.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 Ⅲ
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• pp.1379-1382
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• 2003

Recently, mobile embedded systems used widly in various applications. Managing power consumption is becoming a matter of primary concern because those systems use limited power supply. As an approach reduce power consumption, voltage can be scaled down. according to the execution time and deadline. By reducing the supplying voltage to 1/N power consumption can be reduced to 1/N. DPM-S is a well known method for dynamic voltage scaling. In this paper, we enhanced DPM-S by using average execution time aggressively. The frequency of processor is calculated based in average execution time instead of worst case execution time. Simulation results show that our method achieve up to 5％ energy savings than DPM-S.

• 대한교통학회지
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• 제23권8호
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• pp.113-128
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• 2005

일반적으로 현실(특히 도시) 교통망에서 교차로를 반복해서 방문하는 통행은 존재하지만, 가로를 반복해서 주행하는 현상은 존재하지 않는다. 교통망에서의 루프형 통행은 링크의 반복이 허용되지 않는 링크 비루프(Link Loopless Path) 통행으로 축소된다. 본 연구에서는 K개의 경로탐색에서 기존의 방식과 달리 Heap Ordered Tree를 이용하여 월등한 수행속도(최악의 경우) O(m+ n log n+ K log K)로서 수행되는 Eppstein 알고리즘과 Jimenez et al의 LVEA을 고찰하여, 이들 알고리즘의 문제점인 링크루프의 발생을 제어하는 방안을 제어하도록 한다. 사례연구를 통하여 제안된 알고리즘을 검증 평가한다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.1165-1168
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• 1998

This paper describes a 72-word by 32-bit 2-read/1-write multi-port register file, which is suitable for 32-bit RISC/DSP microprocessors. To minimize area and achieve high speed, advanced single-ended sense amplifiers are used. Each part of circuit is optimized at transistor level. The verification of functionality and timing is performed using HSPICE simulations. After modeling and validating the circuit at transistor level, it was laid out in a 0.6um 1-poly 3-metal layer CMOS technology. The simulation results show maximum operating frequency is 179MHz in worst case conditions. It contains 27,326 transistors and the size is 3.02mm by 2.20mm.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 2003년도 ISIS 2003
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• pp.392-394
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• 2003

There is a well-known simple, stable standard merge algorithm, which uses only linear time but for the price of double space. This extra space consumption has been often remarked as lack of the standard merge sort algorithm that covers a merge process as central operation. In-place merging is a way to overcome this lack and so is a topic with a long tradition of inspection in the area of theoretical computer science. We present an in-place merging algorithm that rear-ranges the elements to be merged by rotation, a special form of block interchanging. Our algorithm is novel, due to its technique of determination of the rotation-areas. Further it has a short and transparent definition. We will give a presentation of our algorithm and prove that it needs in the worst case not more than twice as much comparisons as the standard merge algorithm. Experimental work has shown that our algorithm is efficient and so might be of high practical interest.

• 한국생산제조학회지
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• 제21권2호
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• pp.344-348
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• 2012

The knuckle crane design in Korea has been performed by assuming a cantilever beam type structure and numerically analyzing design data and finally improving the stiffness by replacing material. In our study, a complete finite element model of the knuckle crane is constructed and finite element analysis is conducted using Optistruct. Structural optimization to reduce the weight of the knuckle crane is processed by applying maximum loading condition at the largest radius of motion, which is the worst case of loading condition. As the results, existing over stiff design in a knuckle crane is corrected to meet a desired design limit and overall weight is reduced, which eventually leads to a reduction of $CO_2$ emission.

• International Journal of Aeronautical and Space Sciences
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• 제10권1호
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• pp.37-45
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• 2009

A method of conflict detection and resolution is described by using simple geometric approach. Two VAVs are dealt with and considered as point masses with constant velocity. This paper discusses en route aircraft which are assumed to be linked by real time data bases like ADS-B. With this data base, all DAVs share the information each other. Calculating PCA (Point of Closest Approach), we can evaluate the worst conflict condition between two VAVs. This paper proposes one resolution maneuvering logic, which can be called 'Vector Sharing Resolution'. In case of conflict, using miss distance vector in PCA, we can decide the directions for two VAVs to share the conflict region. With these directions, VAVs are going to maneuver cooperatively. First of all, this paper describes some '2-D' conflict scenarios and then extends to '3-D' conflict scenarios.

• International Journal of Automotive Technology
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• 제6권4호
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• pp.359-365
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• 2005

The absolute longitudinal speed of a vehicle is estimated by using data from an accelerometer of the vehicle and wheel speed sensors of a standard 50-tooth antilock braking system. An intuitive solution to this problem is, 'When wheel slip is low, calculate the vehicle velocity from the wheel speeds; when wheel slip is high, calculate the vehicle speed by integrating signal of the accelerometer.' The speed estimator weighted with fuzzy logic is introduced to implement the above concept, which is formulated as an estimation method. And the method is improved through experiments by how to calculate speed from acceleration signal and slip ratios. It is verified experimentally to usefulness of estimation speed of a vehicle. And the experimental result shows that the estimated vehicle longitudinal speed has only a $6\%$ worst-case error during a hard braking maneuver lasting a few seconds.

• 한국자동차공학회논문집
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• 제10권1호
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• pp.179-186
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• 2002

The absolute longitudinal speed of a vehicle is estimated by using vehicle acceleration data from an accelerometer and wheel speed data from standard 50-tooth antiknock braking system wheel speed sensors. An intuitive solution to this problem is, "When wheel slip is low, calculate absolute velocities from the wheel speeds; when wheel slip is high, calculate absolute velocity by integrating the accelerometer." Fuzzy logic is introduced to implement the above idea and a new algorithm of "modified velocities with step integration" is proposed. This algorithm is verified experimentally to estimate speed of a vehicle, and is also shown to estimate absolute longitudinal vehicle speed with a 6% worst-case error during a hard braking maneuver lasting three seconds.