• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.309-309
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• 2013

기존의 CIGS 태양전지는 window 층(GZO/ZnO/CdS)에서의 투과 및 반사 손실을 줄이기 위하여 MgF2를 이용한 AR (Anti Reflection) 층을 적용하여 cell을 제작하고 있다. 현재 단위공정을 줄이고 시간적 경제적 비용을 절감하기위해 무반사 코팅층 없이 표면의 구조를 변화 시키거나 CIGS 태양전지의 window 층만으로 cell 구조에 적용하는 연구가 많이 진행되고 있다. 본 연구는 AR층과 window층 역할을 동시에 만족하는 일체화된 window층 두께를 설계하고 성장한 후, window층의 열처리 전후의 구조적, 광학적 및 전기적 특성을 비교 평가하였다. Macleod simulation을 이용하여 window 층을 설계한 후, RF magnetron sputtering법을 이용하여 상온성장 시킨 후 N2 분위기에서 후열처리 조건에 따른 박막의 구조적, 전기적 및 광학적 특성을 변화를 X-ray diffractometer, Field emission-scanning electron microscope, Atomic force microscopy, 4 point probe, Hall 측정, 투과도 및 반사도등으로 비교 평가하였다.

• 한국전기전자재료학회논문지
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• 제36권3호
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• pp.226-232
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• 2023

As a potential alternative to flash memory, HfO₂/Al₂O₃ stacks appear to be a viable option as charge capture layers in charge trapping memories. The paper undertakes a review of HfO₂/Al₂O₃ stacks as charge trapping layers, with a focus on comparing the number, thickness, and post-deposition heat treatment and γ-ray and white x-ray treatment of such stacks. Compared to a single HfO₂ layer, the memory window of the 5-layered stack increased by 152.4% after O₂ annealing at ±12 V. The memory window enlarged with the increase in number of layers in the stack and the increase in the Al/Hf content in the stack. Furthermore, our comparison of the treatment of HfO₂/Al₂O₃ stacks with varying annealing temperatures revealed that an increased annealing temperature resulted in a wider storage window. The samples treated with O₂ and subjected to various γ radiation intensities displayed superior resistance. and the memory window increased to 12.6 V at ±16 V for 100 kGy radiation intensity compared to the untreated samples. It has also been established that increasing doses of white x-rays induced a greater number of deep defects. The optimization of stacking layers along with post-deposition treatment condition can play significant role in extending the memory window.

• 한국초전도ㆍ저온공학회논문지
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• 제5권3호
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• pp.11-14
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• 2003

The detailed conditions of dc-sputtering for depositions of yttria-stabilized ZrO$_2$ (YSZ) films were investigated, while the films were grown on the CeO$_2$ template layers on biaxially textured Ni-tapes. The window of oxygen pressures for proper growth of YSZ films, which was dependent on sputtering powers, was determined by sufficient oxidations of the YSZ films and the de-oxidation of the target surface, which was required for rapid sputtering. The window turned out to be fairly wide under certain values of argon pressure. When the sputtering power was raised, the deposition rate increased without narrowing the window. The fabricated YSZ films showed good texture qualities and surface morphologies.

• 한국전기전자재료학회논문지
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• 제16권10호
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• pp.865-870
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• 2003

The MFIS (Metal-Ferroelectric-Insulator-Semiconductor) capacitors were fabricated using a metalorganic decomposition method. Thin layers of CeO$_2$ were deposited as a buffer layer on Si substrate and BLT thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated. X -ray diffraction was used to determine the phase of the BLT thin films and the quality of the CeO$_2$ layer. The morphology of films and the interface structures of the BLT and the CeO$_2$ layers were investigated by scanning electron microscopy. The width of the memory window in the C-V curves for the MFIS structure is 2.82 V. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory FETs with large memory window.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 추계학술대회 논문집 Vol.15
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• pp.186-189
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• 2002

The MFIS capacitors were fabricated using a metalorganic decomposition method. Thin layers of $CeO_2$ were deposited as a buffer layer on Si substrate and BLT thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated. X-ray diffraction was used to determine the phase of the BLT thin films and the quality of the $CeO_2$ layer. The morphology of films and the interface structures of the BLT and the $CeO_2$ layers were investigated by scanning electron microscopy. The width of the memory window in the C-V curves for the MFIS structure is 4.78 V. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory FETs with large memory window.

• ETRI Journal
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• 제35권4호
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• pp.730-733
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• 2013

In this work, buffer layers with various conditions are inserted at an n/i interface in hydrogenated amorphous silicon semitransparent solar cells. It is observed that the performance of a solar cell strongly depends on the arrangement and thickness of the buffer layer. When arranging buffer layers with various bandgaps in ascending order from the intrinsic layer to the n layer, a relatively high open circuit voltage and short circuit current are observed. In addition, the fill factors are improved, owing to an enhanced shunt resistance under every instance of the introduced n/i buffer layers. Among the various conditions during the arrangement of the buffer layers, a reverse V shape of the energy bandgap is found to be the most effective for high efficiency, which also exhibits intermediate transmittance among all samples. This is an inspiring result, enabling an independent control of the conversion efficiency and transmittance.

• Current Photovoltaic Research
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• 제2권3호
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• pp.103-109
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• 2014

Highly efficient hydrogenated nanocrystalline silicon (nc-Si:H) thin-film solar cells were prepared on flexible stainless steel substrates using plasma-enhanced chemical vapor deposition. To enhance the performance of solar cells, material properties of back reflectors, n-doped seed layers and wide bandgap nc-SiC:H window layers were optimized. The light scattering efficiency of Ag back reflectors was improved by increasing the surface roughness of the films deposited at elevated substrate temperatures. Using the n-doped seed layers with high crystallinity, the initial crystal growth of intrinsic nc-Si:H absorber layers was improved, resulting in the elimination of the defect-dense amorphous regions at the n/i interfaces. The nc-SiC:H window layers with high bandgap over 2.2 eV were deposited under high hydrogen dilution conditions. The vertical current flow of the films was enhanced by the formation of Si nanocrystallites in the amorphous SiC:H matrix. Under optimized conditions, a high conversion efficiency of 9.13% ($V_{oc}=0.52$, $J_{sc}=25.45mA/cm^2$, FF = 0.69) was achieved for the flexible nc-Si:H thin-film solar cells.

• 한국재료학회지
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• 제19권9호
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• pp.462-467
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• 2009

The Charge Trap Flash (CTF) memory device is a replacement candidate for the NAND Flash device. In this study, Pt/$Al_2O_3/La_2O_3/SiO_2$/Si multilayer structures with lanthanum oxide charge trap layers were fabricated for nonvolatile memory device applications. Aluminum oxide films were used as blocking oxides for low power consumption in program/erase operations and reduced charge transports through blocking oxide layers. The thicknesses of $SiO_2$ were from 30 $\AA$ to 50 $\AA$. From the C-V measurement, the largest memory window of 1.3V was obtained in the 40 $\AA$ tunnel oxide specimen, and the 50 $\AA$ tunnel oxide specimen showed the smallest memory window. In the cycling test for reliability, the 30 $\AA$ tunnel oxide sample showed an abrupt memory window reduction due to a high electric field of 9$\sim$10MV/cm through the tunnel oxide while the other samples showed less than a 10% loss of memory window for $10^4$ cycles of program/erase operation. The I-V measurement data of the capacitor structures indicated leakage current values in the order of $10^{-4}A/cm^2$ at 1V. These values are small enough to be used in nonvolatile memory devices, and the sample with tunnel oxide formed at $850^{\circ}C$ showed superior memory characteristics compared to the sample with $750^{\circ}C$ tunnel oxide due to higher concentration of trap sites at the interface region originating from the rough interface.

• 설비공학논문집
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• 제27권9호
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• pp.463-467
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• 2015

The air-bubble sheet has been widely used to wrap fragile products for long-distance transportation. The further usage of the air-bubble sheet as a thermal-insulation material for the reduction of the thermal conductivities of window systems has occurred because of its low price, in addition to its thermal-conductivity properties. In this study, the thermal performances of a variety of commercial air-bubble sheets according to various applications were evaluated. The experiments were performed with single-glazed and double-glazed windows and three types of air-bubble sheets of different air volumes. U-values are used and were calculated for the determination of the thermal performances that are based on the KS F 2278. The maximum decrease of the U-value was measured as 1.092 when a sheet was attached onto the frame of single-glazed window. The square-like air-bubble sheet that contains the largest air volume shows the highest thermal-resistance value. Double layers of the air-bubble sheets show better performances than those of the single layers on both sides of the windows.

• 대한금속재료학회지
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• 제48권3호
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• pp.256-261
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• 2010

In this work, high-k dielectric stacks of $HfO_2$ and $HfO_2$/$Al_2O_3$/$HfO_2$ (HAH) were deposited on $SiO_2/Si$ substrates by atomic layer deposition as charge trapping layers in charge trapping devices. The structural stability and the charge trapping characteristics of such stacks were investigated using Metal-Alumina-Hafnia-Oxide-Silicon (MAHOS) structure. The surface roughness of $HfO_2$ was stable up to 11 nm with the insertion of 0.2 nm thick $Al_2O_3$. The effect of the thickness of the HAH stack and the thickness of intermediate $Al_2O_3$ on charge trapping characteristics were investigated for MAHOS structure under various gate bias pulse with duration of 100 ms. The threshold voltage shift after programming and erase showed that the memory window was increased with increasing bias on gate. However, the programming window was independent of the thickness of HAH charge trapping layers. When the thickness of $Al_2O_3$insertion increased from 0.2 nm to 1 nm, the erase window was decreased without change in the programming window.