• Title/Summary/Keyword: Window layer

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Formation of Sn Through-Silicon-Via and Its Interconnection Process for Chip Stack Packages (칩 스택 패키지용 Sn 관통-실리콘-비아 형성공정 및 접속공정)

  • Kim, Min-Young;Oh, Taek-Soo;Oh, Tae-Sung
    • Korean Journal of Metals and Materials
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    • v.48 no.6
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    • pp.557-564
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    • 2010
  • Formation of Sn through-silicon-via (TSV) and its interconnection processes were studied in order to form a three-dimensional interconnection structure of chip-stack packages. Different from the conventional formation of Cu TSVs, which require a complicated Cu electroplating process, Sn TSVs can be formed easily by Sn electroplating and reflow. Sn via-filling behavior did not depend on the shape of the Sn electroplated layer, allowing a much wider process window for the formation of Sn TSVs compared to the conventional Cu TSV process. Interlocking joints were processed by intercalation of Cu bumps into Sn vias to form interconnections between chips with Sn TSVs, and the mechanical integrity of the interlocking joints was evaluated with a die shear test.

Benchmarking of Single Image Reflection Removal Algorithms (단일 영상의 반사된 이미지 제거에 대한 벤치마킹 실험)

  • Lee, Yong-Hwan;Kim, Youngseop
    • Journal of the Semiconductor & Display Technology
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    • v.18 no.4
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    • pp.154-159
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    • 2019
  • Undesirable negative image is occurred in photographs taken across partial reflections such as glass window and electronic display. Efficient removing reflections given a single image are in the spotlight in recent researches. This paper discusses and evaluates two published image reflection removal algorithms, and compares the performance of time and quality of those methods with a common dataset. As benchmarking test cases are presented, we propose to modify one of the methods to reduce the run-time with small effects on the similar image quality.

A Study on Performance Evaluation based on Packet Dropping in ATM Network . New Scheme Proposal

  • Park, Seung-Seob;Yuk, Dong-Cheol
    • Journal of Navigation and Port Research
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    • v.27 no.3
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    • pp.283-288
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    • 2003
  • Recently, the growth of applications and services over high-speed Internet increases, ATM networks as wide area back-bone has been a major solution. As the conventional TCP/IP suite is still the standard protocol used to support upper application on current. Internet, the issues regarding whether TCP/IP will operate efficiently on top of an ATM infrastructure and how to control its QoS still remain for studies. TCP uses a window-based protocol for flow control in the transport layer. When TCP uses the UBR service in ATM layer, the control method is only buffer management. If a cell is discarded in ATM layer, one whole packet of TCP will be lost; this fact occur the most TCP performance degradation. Several dropping strategies, such as Tail Drop, EPD, PPD, SPD, FBA, have been proposed to improve the TCP performance over ATM. In this paper, to improve the TCP performance, we propose a packet dropping scheme that is based on comparison with EPD, SPD and FBA. Our proposed scheme is applied to schemes discussed in the previous technology. Our proposed scheme does not need to know each connection's mean packet size. When the buffer exceeds the given threshold, it is based on comparison between the number of dropped packet and the approved packet. Our results are reported and discussed for comparing these discarding schemes under similar conditions. Although the number of virtual channel (VC) is increased, the simulation results showed that the proposed scheme can allocate more fairly each VC than other scheme.

Design for a Single-layer Feeder Waveguide Array using $\pi$-Junctions with the Inductive Wall (유도성 벽을 이용한 $\pi$ 분기형 일층구조 급전도파관 어레이의 설계)

  • 민경식;김광욱;김동철;임학규
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.12 no.2
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    • pp.257-267
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    • 2001
  • This paper presents a design for a single-layer feeder waveguide array using $\pi$-junctions with the inductive wall. The feed structure consists of a single waveguide placed on the same layer as radiating waveguide and is characterized by the unit divider, called a $\pi$-junction. This $\pi$-junction with an inductive wall splits part of the power into two branchs waveguide through one coupling window, and can excite densely arrayed waveguide at equal phase and amplitude. The power dividing characteristics of the cascade of $\pi$ -junctions are analyzed by Galerkin's method of moments. The numerical results show reasonable agreement with the experimental results. From the optimum simulation results based on the feeder waveguide using $\pi$-junction, we obtained the scattering matrices of the feeder divided power at 3.95 GHz.

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Basic characteristics of metal-ferroelectric-insulator-semiconductor structure using a high-k PrOx insulator layer

  • Noda, Minoru;Kodama, Kazushi;Kitai, Satoshi;Takahashi, Mitsue;Kanashima, Takeshi;Okuyama, Masanori
    • Electrical & Electronic Materials
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    • v.16 no.9
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    • pp.64.1-64
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    • 2003
  • A metal-ferroelectric [SrBi$_2$Ta$_2$O$\_$9/ (SBT)-high-k-insulator(PrOx)-semiconductor(Si) structure has been fabricated and evaluated as a key part of metal-ferroelectric-insulator-semiconductor-field-effect-transistor MFIS-FET memory, aiming to improve the memory retention characteristics by increasing the dielectric constant in the insulator layer and suppressing the depolarization field in the SBT layer. A 20-nm PrOx film grown on Si(100) showed both a high of about 12 and a low leakage current density of less than 1${\times}$ 10e-8 A/$\textrm{cm}^2$ at 105 MV/cm. A 400-nm SBT film prepared on PrOx/Si shows a preferentially oriented (105) crystalline structure, grain size of about 130 nm and subface roughness of 3.2 nm. A capacitance-voltage hysteresis is confirmed on the Pt/SBT/PrOx/Si diode with a memory window of 0.3V at a sweep voltage width of 12 V. The memory retention time was about 1 104s, comparable to the conventional Pt/SBT/SiO$\_$x/N$\_$y/(SiO$\_$N/)/Si. The gradual change of the capacitance indicates that some memory degradation mechanism is different from that in the Pt/SBT/SiON/Si structure.

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3-D Structured Cu2ZnSn (SxSe1-x)4 (CZTSSe) Thin Film Solar Cells by Mo Pattern using Photolithography (Mo 패턴을 이용한 3-D 구조의 Cu2ZnSn (SxSe1-x)4 (CZTSSe) 박막형 태양전지 제작)

  • Jo, Eunjin;Gang, Myeng Gil;Shin, hyeong ho;Yun, Jae Ho;Moon, Jong-ha;Kim, Jin Hyeok
    • Current Photovoltaic Research
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    • v.5 no.1
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    • pp.20-24
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    • 2017
  • Recently, three-dimensional (3D) light harvesting structures are highly attracted because of their high light harvesting capacity and charge collection efficiencies. In this study, we have fabricated $Cu_2ZnSn(S_xSe_{1-x})_4$ based 3D thin film solar cells on PR patterned Molybdenum (Mo) substrates using photolithography technique. Specifically, Mo patterns were deposited on PR patterned Mo substrates by sputtering and the thin Cu-Zn-Sn stacked layer was deposited over this Mo patterns by sputtering technique. The stacked Zn-Sn-Cu precursor thin films were sulfo-selenized to form CZTSSe pattern. Finally, CZTSSe absorbers were coated with thin CdS layer using chemical bath deposition and ZnO window layer was deposited over CZTSSe/CdS using DC sputtering technique. Fabricated 3-D solar cells were characterized by X-ray diffraction (XRD), X-ray fluorescence (XRF) analysis, Field-emission scanning electron microscopy (FE-SEM) to study their structural, compositional and morphological properties, respectively. The 3% efficiency is achieved for this kind of solar cell. Further efforts will be carried out to improve the performance of solar cell through various optimizations.

Design and Evaluations of Underwater Hydrophone with Self Noise Suppressing Structures; - Part Ⅱ. Influence of Acostic Damping Layer Properties - (저 잡음 수중 청음기의 설계 방안 연구 - Ⅱ. 음향 감쇠층 재질의 영향 -)

  • Im, Jong-In;Roh, Young-Rae
    • The Journal of the Acoustical Society of Korea
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    • v.16 no.3
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    • pp.13-17
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    • 1997
  • This paper investigates the influence of material properties of the acoustic damping layer in the low noise hydrophone designed in the previous paper. For increase of the insensitivity of the hydrophone to external noises, acoustic impedance and damping coefficients are selected and the effects of the selected material property on the hydrophone response to the external noises are simulated with finite element method (FEM). The results show that the damping coefficients are not influential to the structural vibration decoupling from the sensing element. On the other hand, the optimum acoustic impedance of compliant layer is estimated which is smaller than 1 Mrayl or larger than 4 Mrayl. However polymer materials, which are in general use for acoustic window and damping layers, is not appropriate for the compliant materials of this hydrophone. Therefore development of new composite materials, i.e. ceramic-polymer composite or metal-ceramic composites etc., is required for the development of effective self noise suppressing underwater hydrophones.

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Decrease of Interface Trap Density of Deposited Tunneling Layer Using CO2 Gas and Characteristics of Non-volatile Memory for Low Power Consumption (CO2가스를 이용하여 증착된 터널층의 계면포획밀도의 감소와 이를 적용한 저전력비휘발성 메모리 특성)

  • Lee, Sojin;Jang, Kyungsoo;Nguyen, Cam Phu Thi;Kim, Taeyong;Yi, Junsin
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.29 no.7
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    • pp.394-399
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    • 2016
  • The silicon dioxide ($SiO_2$) was deposited using various gas as oxygen and nitrous oxide ($N_2O$) in nowadays. In order to improve electrical characteristics and the interface state density ($D_{it}$) in low temperature, It was deposited with carbon dioxide ($CO_2$) and silane ($SiH_4$) gas by inductively coupled plasma chemical vapor deposition (ICP-CVD). Each $D_{it}$ of $SiO_2$ using $CO_2$ and $N_2O$ gas was $1.30{\times}10^{10}cm^{-2}{\cdot}eV^{-1}$ and $3.31{\times}10^{10}cm^{-2}{\cdot}eV^{-1}$. It showed $SiO_2$ using $CO_2$ gas was about 2.55 times better than $N_2O$ gas. After 10 years when the thin film was applied to metal/insulator/semiconductor(MIS)-nonvolatile memory(NVM), MIS NVM using $SiO_2$($CO_2$) on tunneling layer had window memory of 2.16 V with 60% retention at bias voltage from +16 V to -19 V. However, MIS NVM applied $SiO_2$($N_2O$) to tunneling layer had 2.48 V with 61% retention at bias voltage from +20 V to -24 V. The results show $SiO_2$ using $CO_2$ decrease the $D_{it}$ and it improves the operating voltage.

The Study on the Quantitative Dust Index Using Geostationary Satellite (정지기상위성 자료를 이용한 정량적 황사지수 개발 연구)

  • Kim, Mee-Ja;Kim, Yoonjae;Sohn, Eun-Ha;Kim, Kum-Lan;Ahn, Myung-Hwan
    • Atmosphere
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    • v.18 no.4
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    • pp.267-277
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    • 2008
  • The occurrence and strength of the Asian Dust over the Korea Peninsular have been increased by the expansion of the desert area. For the continuous monitoring of the Asian Dust event, the geostationary satellites provide useful information by detecting the outbreak of the event as well as the long-range transportation of dust. The Infrared Optical Depth Index (IODI) derived from the MTSAT-1R data, indicating a quantitative index of the dust intensity, has been produced in real-time at Korea Meteorological Administration (KMA) since spring of 2007 for the forecast of Asian dust. The data processing algorithm for IODI consists of mainly two steps. The first step is to detect dust area by using brightness temperature difference between two thermal window channels which are influenced with different extinction coefficients by dust. Here we use dynamic threshold values based on the change of surface temperature. In the second step, the IODI is calculated using the ratio between current IR1 brightness temperature and the maximum brightness temperature of the last 10 days which we assume the clear sky. Validation with AOD retrieved from MODIS shows a good agreement over the ocean. Comparison of IODI with the ground based PM10 observation network in Korea shows distinct characteristics depending on the altitude of dust layer estimated from the Lidar data. In the case that the altitude of dust layer is relatively high, the intensity of IODI is larger than that of PM10. On the other hand, when the altitude of dust layer is lower, IODI seems to be relatively small comparing with PM10 measurement.

Atomic layer deposition of In-Sb-Te Thin Films for PRAM Application

  • Lee, Eui-Bok;Ju, Byeong-Kwon;Kim, Yong-Tae
    • Proceedings of the Korean Vacuum Society Conference
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    • 2011.02a
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    • pp.132-132
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    • 2011
  • For the programming volume of PRAM, Ge2Sb2Te5(GST) thin films have been dominantly used and prepared by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD). Among these methods, ALD is particularly considered as the most promising technique for the integration of PRAM because the ALD offers a superior conformality to PVD and CVD methods and a digital thickness control precisely to the atomic level since the film is deposited one atomic layer at a time. Meanwhile, although the IST has been already known as an optical data storage material, recently, it is known that the IST benefits multistate switching behavior, meaning that the IST-PRAM can be used for mutli-level coding, which is quite different and unique performance compared with the GST-PRAM. Therefore, it is necessary to investigate a possibility of the IST materials for the application of PRAM. So far there are many attempts to deposit the IST with MOCVD and PVD. However, it has not been reported that the IST can be deposited with the ALD method since the ALD reaction mechanism of metal organic precursors and the deposition parameters related with the ALD window are rarely known. Therefore, the main aim of this work is to demonstrate the ALD process for IST films with various precursors and the conformal filling of a nano size programming volume structure with the ALD?IST film for the integration. InSbTe (IST) thin films were deposited by ALD method with different precursors and deposition parameters and demonstrated conformal filling of the nano size programmable volume of cell structure for the integration of phase change random access memory (PRAM). The deposition rate and incubation time are 1.98 A/cycle and 25 cycle, respectively. The complete filling of nano size volume will be useful to fabricate the bottom contact type PRAM.

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