• ETRI Journal
• /
• v.42 no.5
• /
• pp.773-780
• /
• 2020

A 40 nm complementary metal oxide semiconductor carrier-aggregated drive amplifier with high linearity is presented for sub-GHz Internet of Things applications. The proposed drive amplifier consists of two high linear amplifiers, which are composed of five differential cascode cells. Carrier aggregation can be achieved by switching on both the driver amplifiers simultaneously and combining the two independent signals in the current mode. The common gate bias of the cascode cells is selected to maximize the output 1 dB compression point (P1dB) to support high-linear wideband applications, and is used for the local supply voltage of digital circuitry for gain control. The proposed circuit achieved an output P1dB of 10.7 dBm with over 22.8 dBm of output 3rd-order intercept point up to 0.9 GHz and demonstrated a 55 dBc adjacent channel leakage ratio (ACLR) for the 802.11af with -5 dBm channel power. To the best of our knowledge, this is the first demonstration of the wideband carrier-aggregated drive amplifier that achieves the highest ACLR performance.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.12 no.1
• /
• pp.37-43
• /
• 2001

In this paper, we designed a linear power amplifier considering its delay characteristics fur wideband operation. The power amplifier has the gain of 37 dB and is designed in 3-stage typ with 1W output power. The error amplifier has the gain of 55 dB and is designed in 4-stage typ. And directional coupler and power divider are designed. Vector modulator is used to adjust magnitude and phase of signal. A linear power amplifier, that is assembled with each modules, is designed considering the delay characteristics for 2.11~2.2 GHz. Its C/I3 ratio has been improved by B5 dB for bandwidth of 30 MHz.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.19 no.11
• /
• pp.2238-2248
• /
• 1994

In this paper, we analyze a Microwave Amplifier Ultra-Wideband charateristic to apply Multi-Giga b/s optical receiver preamplifier in high speed optical communication system. To obtain frequency expanding effect. we analyze the frequency gain degradation effects of capacitances in the GaAs MESFET small-signal equivalent circuit and design Feedback amplifier Module(FAM) which has inductor peaking elements to compensate its effects and to expand frequency band. We derive optimum inductor peaking values in order to get flat gain in frequency band. The input and the output impedances of FAM are matched by Real Frequency Method and we design one and two stage ultra wideband microwave amplifier. With simulation results, it show $6.36\sim6.86dB$ and $9.1\sim10.3dB$ gains and execllent gain flatness in $0.5\sim12GHz$ respectively.

• Journal of electromagnetic engineering and science
• /
• v.5 no.3
• /
• pp.112-116
• /
• 2005

This paper presents a broadband two-stage low noise amplifier(LNA) operating from 3 to 10 GHz, designed with 0.18 ${\mu}m$ RF CMOS technology, The cascode feedback topology and broadband matching technique are used to achieve broadband performance and input/output matching characteristics. The proposed UWB LNA results in the low noise figure(NF) of 3.4 dB, input/output return loss($S_{11}/S_{22}$) of lower than -10 dB, and power gain of 14.5 dB with gain flatness of $\pm$1 -dB within the required bandwidth. The input-referred third-order intercept point($IIP_3$) and the input-referred 1-dB compression point($P_{ldB}$) are -7 dBm and -17 dBm, respectively.

• Proceedings of the KIEE Conference
• /
• 2007.10a
• /
• pp.193-194
• /
• 2007

This paper presents the design of a power amplifier for full-band UWB application systems using a CMOS 0..18um technology. A wideband RLC filter and a multilevel RLC matching scheme are utilized to achieve the wideband input/output matching. Both the cascade and cascode stage are used to increase the gain and to achieve gain flatness. Simulation results show that the designed amplifier provides a power gain greater than 10 dB throughout the UWB full-band(3.1-10.6GHz) and an input P1dB of -1.2dBm at 6.9GHz. It consumes 35.8mW from a 1.8V supply.

• ETRI Journal
• /
• v.29 no.5
• /
• pp.670-672
• /
• 2007

An ultra-wideband low-noise amplifier is proposed with operation up to 8.2 GHz. The amplifier is fabricated with a 0.18-${\mu}m$ CMOS process and adopts a two-stage cascode architecture and a simplified Chebyshev filter for high gain, wide band, input-impedance matching, and low noise. The gain of 19.2 dB and minimum noise figure of 3.3 dB are measured over 3.4 to 8.2 GHz while consuming 17.3 mW of power. The Proposed UWB LNA achieves a measured power-gain bandwidth product of 399.4 GHz.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.10 no.1
• /
• pp.13-20
• /
• 2015

Existing LDMOS power amplifier that used class-AB and doherty system shows 55% of efficiency in 60MHz narrow band. Because RRH has been applied to power amplifier at base station. It is required that over 100MHz expanded band and more than 60% high efficiency power amplifier. In this paper we designed class-J power amplifier using LDMOS FET which has over 60% high efficiency characteristic in 200MHz. The output matching circuit of designed class-J power amplifier has been optimized to contain pure reactance at second harmonic load and has low quality factor Q. As a measurement result of the amplifier, when we input continuous wave signal, we checked 62~70% of power added efficiency(PAE) in 2.06~2.2GHz including WCDMA frequency as a 10W class-J power amplifier.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.28 no.2
• /
• pp.105-112
• /
• 2017

In order to satisfy the diffusion of multimedia service in mobile communication and the demand for high-speed communication, it is essential to modify and improve high efficiency, wideband and nonlinear characteristic of multiband power amplifier. This research is designed to implement a single-stub matching circuit as a 2nd harmonic one that meets conditions of the Class-J power amplifier. Low characteristic impedance of the single-stub line is necessary to suit conditions of wideband Class-J. This research uses ceramic substrates having high permittivity to implement the single-stub line with low characteristic impedance, which eventually results in an amplifier satisfying the output impedance terms of Class-J in wideband frequency range. This result attributes to use of GaN HEMT packaged with a 2nd harmonic matching circuit and external fundamental circuit. The measurement results of the Class-J amplifier confirms the following characteristics: more than output power of 50 W(47 dBm) in bandwidth of 1.8~2.7 GHz(0.9GHz), maximum drain efficiency of 72.6 %, and maximum PAE characteristic of 66.5 %.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.29 no.5
• /
• pp.397-400
• /
• 2018

This paper presents a miniaturized 65 nm CMOS 30~46 GHz wideband amplifier. To minimize the chip area, coupled inductors are used in the matching networks. The measurement shows that the fabricated amplifier exhibits 9.3 dB of peak gain, 16 GHz of 3 dB bandwidth, and 42 % fractional bandwidth. The measured input and output return losses were more than 10 dB at 35.8~46.0 GHz and 28.6~37.8 GHz, respectively. The chip consumes 42 mW at 1.2 V. The measured group delay variation is 19.1 ps within the 3 dB bandwidth and the chip size excluding the pads is $0.09mm^2$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.26 no.7
• /
• pp.620-626
• /
• 2015

In this paper, a 2~6 GHz wideband GaN power amplifier MMIC is designed and fabricated using a second-order all-pass filter for input impedance matching and an LC parallel resonant circuit for minimizing an output reactance component of the transistor. The second-order all-pass filter used for wideband lossy matching is modified in an asymmetric configuration to compensate the effect of channel resistance of the GaN transistor. The power amplifier MMIC chip that is fabricated using a $0.25{\mu}m$ GaN HEMT foundry process of Win Semiconductors, Corp. is $2.6mm{\times}1.3mm$ and shows a flat linear gain of about 13 dB and input return loss of larger than 10 dB. Under a saturated power mode, it also shows output power of 38.6~39.8 dBm and a power-added efficiency of 31.3~43.4 % in 2 to 6 GHz.