• 한국재료학회지
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• 제33권8호
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• pp.344-351
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• 2023

Cesium lead iodide (CsPbI₃) with a bandgap of ~1.7 eV is an attractive material for use as a wide-gap perovskite in tandem perovskite solar cells due to its single halide component, which is capable of inhibiting halide segregation. However, phase transition into a photo inactive δ-CsPbI₃ at room temperature significantly hinders performance and stability. Thus, maintaining the photo-active phase is a key challenge because it determines the reliability of the tandem device. The dimethylammonium (DMA)-facilitated CsPbI₃, widely used to fabricate CsPbI₃, exhibits different phase transition behaviors than pure CsPbI₃. Here, we experimentally investigated the phase behavior of DMA-facilitated CsPbI₃ when exposed to external factors, such as heat and moisture. In DMA-facilitated CsPbI₃ films, the phase transition involving degradation was observed to begin at a temperature of 150 ℃ and a relative humidity of 65 %, which is presumed to be related to the sublimation of DMA. Forming a closed system to inhibit the sublimation of DMA significantly improved the phase transition under the same conditions. These results indicate that management of DMA is a crucial factor in maintaining the photo-active phase and implies that when employing DMA designs are necessary to ensure phase stability in DMA-facilitated CsPbI₃ devices.

• 접착 및 계면
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• 제24권2호
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• pp.60-63
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• 2023

AlGaN/GaN 이종접합 구조는 이차원 전자 가스층(2-DEG)으로 인해 높은 전자이동도를 갖고 있으며, 넓은 밴드갭을 갖기 때문에 고온에서 높은 항복전압을 갖는 특성을 가지고 있어, 고전력, 고주파 전자 소자로 주목받고 있다. 이러한 이점을 갖고 있음에도 불구하고, 전류 붕괴 등의 다양한 소자 신뢰성에 영향을 주는 인자들이 있기 때문에 이를 해결하고자, 본 논문에서는 금속-유기-화학기상증착법을 이용하여 AlGaN/GaN 이종 접합구조와 SiN 패시베이션 층을 연속 증착시켰다. 이를 통해 HEMTs소자에 SiN패시베이션이 미치는 재료 특성 및 전기적 특성을 분석했으며, 결과를 바탕으로 저주파 잡음 특성을 측정해 소자의 전도 메커니즘 모델과 채널 내의 결함의 원인에 대해서 분석하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.55-55
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• 2009

Silicon Carbide (SiC) is a material with a wide bandgap (3.26eV), a high critical electric field (~2.3MV/cm), a and a high bulk electron mobility (${\sim}900cm^2/Vs$). These electronic properties allow high breakdown voltage, high frequency, and high temperature operation compared to Silicon devices. Although various SiC DMOSFET structures have been reported so far for optimizing performances. the effect of channel dimension on the switching performance of SiC DMOSFETs has not been extensively examined. In this paper, we report the effect of the interface states ($Q_s$) on the transient characteristics of SiC DMOSFETs. The key design parameters for SiC DMOSFETs have been optimized and a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. has been used to understand the relationship with the switching characteristics. To investigate transient characteristic of the device, mixed-mode simulation has been performed, where the solution of the basic transport equations for the 2-D device structures is directly embedded into the solution procedure for the circuit equations. The result is a low-loss transient characteristic at low $Q_s$. Based on the simulation results, the DMOSFETs exhibit the turn-on time of 10ns at short channel and 9ns at without the interface charges. By reducing $SiO_2/SiC$ interface charge, power losses and switching time also decreases, primarily due to the lowered channel mobilities. As high density interface states can result in increased carrier trapping, or recombination centers or scattering sites. Therefore, the quality of $SiO_2/SiC$ interfaces is important for both static and transient properties of SiC MOSFET devices.

• 한국결정성장학회지
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• 제27권6호
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• pp.275-281
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• 2017

AlN는 넓은 밴드 갭 및 높은 열전도율로 인해 넓은 밴드 갭 및 고주파 전자 소자로 유망한 재료이다. AlN은 전력 반도체의 재료로서 더 큰 항복전압과 고전압에서의 더 작은 특성저항의 장점을 가지고 있다. 높은 전도도를 갖는 p형 AlN 에피층의 성장은 AlN 기반 응용 제품 제조에 중요하다. 본 논문에서는 Mg이 도핑된 AlN 에피층을 혼합 소스 HVPE에 의해 성장하였다. Al 및 Mg 혼합 금속은 Mg-doped AlN 에피 층의 성장을 위한 소스 물질로 사용하였다. AlN 내의 Mg 농도는 혼합 소스에서 Mg 첨가 질량의 양을 조절함으로써 제어되었다. 다양한 Mg 농도를 갖는 AlN 에피 층의 표면 형태 및 결정 구조는 FE-SEM 및 HR-XRD에 의해 조사하였다. Mg-doped AlN 에피 층의 XPS 스펙트럼으로 부터 혼합 소스 HVPE에 의해 Mg을 AlN 에피 층에 도핑할 수 있음을 증명하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.11-11
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• 2010

Thin-film-transistors (TFTs) that can be deposited at low temperature have recently attracted lots of applications such as sensors, solar cell and displays, because of the great flexible electronics and transparent. Transparent and flexible transistors are being required that high mobility and large-area uniformity at low temperature [1]. But, unfortunately most of TFT structures are used to be $SiO_2$ as gate dielectric layer. The $SiO_2$ has disadvantaged that it is required to high driving voltage to achieve the same operating efficiency compared with other high-k materials and its thickness is thicker than high-k materials [2]. To solve this problem, we find lots of high-k materials as $HfO_2$, $ZrO_2$, $SiN_x$, $TiO_2$, $Al_2O_3$. Among the High-k materials, $Al_2O_3$ is one of the outstanding materials due to its properties are high dielectric constant ( ~9 ), relatively low leakage current, wide bandgap ( 8.7 eV ) and good device stability. For the realization of flexible displays, all processes should be performed at very low temperatures, but low temperature $Al_2O_3$ grown by sputtering showed deteriorated electrical performance. Further decrease in growth temperature induces a high density of charge traps in the gate oxide/channel. This study investigated the effect of growth temperatures of ALD grown $Al_2O_3$ layers on the TFT device performance. The ALD deposition showed high conformal and defect-free dielectric layers at low temperature compared with other deposition equipments [2]. After ITO was wet-chemically etched with HCl : $HNO_3$ = 3:1, $Al_2O_3$ layer was deposited by ALD at various growth temperatures or lift-off process. Amorphous InGaZnO channel layers were deposited by rf magnetron sputtering at a working pressure of 3 mTorr and $O_2$/Ar (1/29 sccm). The electrodes were formed with electron-beam evaporated Ti (30 nm) and Au (70 nm) bilayer. The TFT devices were heat-treated in a furnace at $300^{\circ}C$ and nitrogen atmosphere for 1 hour by rapid thermal treatment. The electrical properties of the oxide TFTs were measured using semiconductor parameter analyzer (4145B), and LCR meter.

• 한국전기전자재료학회논문지
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• 제35권6호
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• pp.603-609
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• 2022

Passivation quality is mainly governed by epitaxial growth of crystalline silicon wafer surface. Void-rich intrinsic a-Si:H interfacial layer could offer higher resistivity of the c-Si surface and hence a better device efficiency as well. To reduce the resistivity of the contact area, a modification of void-rich intrinsic layer of a-Si:H towards more ordered state with a higher density is adopted by adapting its thickness and reducing its series resistance significantly, but it slightly decreases passivation quality. Higher resistance is not dominated by asymmetric effects like different band offsets for electrons or holes. In this study, multilayer of intrinsic a-Si:H layers were used. The first one with a void-rich was a-Si:H(I₁) and the next one a-SiO_x:H(I₂) were used, where a-SiO_x:H(I₂) had relatively larger band gap of ~2.07 eV than that of a-Si:H (I₁). Using a-SiO_x:H as I₂ layer was expected to increase transparency, which could lead to an easy carrier transport. Also, higher implied voltage than the conventional structure was expected. This means that the a-SiO_x:H could be a promising material for a high-quality passivation of c-Si. In addition, the i-a-SiO_x:H microstructure can help the carrier transportation through tunneling and thermal emission.