• JSTS:Journal of Semiconductor Technology and Science
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• 제12권4호
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• pp.418-425
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• 2012

In this paper, efficient implementation of error correction code (ECC) processing circuits based on single error correction and double error detection (SEC-DED) code with check bit pre-computation is proposed for memories. During the write operation of memory, check bit pre-computation eliminates the overall bits computation required to detect a double error, thereby reducing the complexity of the ECC processing circuits. In order to implement the ECC processing circuits using the check bit pre-computation more efficiently, the proper SEC-DED codes are proposed. The H-matrix of the proposed SEC-DED code is the same as that of the odd-weight-column code during the write operation and is designed by replacing 0's with 1's at the last row of the H-matrix of the odd-weight-column code during the read operation. When compared with a conventional implementation utilizing the odd-weight- column code, the implementation based on the proposed SEC-DED code with check bit pre-computation achieves reductions in the number of gates, latency, and power consumption of the ECC processing circuits by up to 9.3%, 18.4%, and 14.1% for 64 data bits in a word.

• 대한전자공학회논문지SD
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• 제39권9호
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• pp.37-44
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• 2002

학습된 신경망(Pre-trained neural network)은 고정된 가중치(weight)를 갖는다. 이 논문에서는 이러한 특성을 이용하여 신경망의 효과적인 디지털 하드웨어의 설계방법을 제안한다. 이를 위해 신경망의 PEs(Processing Elements)연산은 행렬-벡터 곱셈으로 표하고 고정된 가중치와 입력 데이터의 관계를 비트-레벨 어레이(array) 구조로 표현하여, 노드 소거와 가중치 비트 패턴에 따른 공유 노드 설정을 통한 최적화로 연산에 필요한 노드를 최소화한다. FPGA 시뮬레이션 결과, 완전한 정확성에 기반한 하드웨어를 설계하는 경우, 하드웨어 비용을 상당부분 줄였고 동작 주파수가 높다는 것을 확인하였다. 또한, 제안한 설계방법은 한정된 공간 내에서 많은 수의 PEs 구현이 가능함으로, 큰 신경망 모델에 대한 온-칩(on-chip) 구현이 가능하다.

• 전자공학회논문지A
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• 제31A권3호
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• pp.28-39
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• 1994

We experimented on memory multichip modules to increase the packing density of memory devices and to improve their electrical characteristics. A 128K$\times$8bit SRAM module was made of four 32K$\times$8bit SRAM memory chips. The memory multichip module was constructed on a low-cost double sided PCB(printed circuit boared) substrate. In the process of fabricating a multichip module. we focused on the improvement of its electrical characteristics. volume, and weight by employing bare memory chips. The characteristics of the bare chip module was compared with that of the module with four packaged chips. We conducted circuit routing with a PCAD program, and found the followings: the routed area for the module with bare memory chips reduced to a quarter of that area for module with packaged memory chips. 1/8 in volume, 1/5 in weight. Signal transmission delay times calculated by using transmission line model was reduced from 0.8 nsec to 0.4 nsec only on the module board, but the coupling coefficinet was not changed. Thus, we realized that the electrical characteristics of multichip packages on PCB board be improved greatly when using bare memory chips.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제12권7호
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• pp.3455-3474
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• 2018

As a unique form of signed-digit representation, non-adjacent form (NAF) minimizes Hamming weight by removing a stream of non-zero bits from the binary representation of positive integer. Thanks to this strong point, NAF has been used in various applications such as cryptography, packet filtering and so on. In this paper, to improve the NAF conversion speed of the $NAF_w$ algorithm, we propose a new NAF conversion algorithm, called w-bit Shifting Non-Adjacent Form($SNAF_w$), where w is width of scanning window. By skipping some unnecessary bit comparisons, the proposed algorithm improves the NAF conversion speed of the $NAF_w$ algorithm. To verify the excellence of the $SNAF_w$ algorithm, the $NAF_w$ algorithm and the $SNAF_w$ algorithm are implemented in the 8-bit microprocessor ATmega128. By measuring CPU cycle counter for the NAF conversion under various input patterns, we show that the $SNAF_2$ algorithm not only increases the NAF conversion speed by 24% on average but also reduces deviation in the NAF conversion time for each input pattern by 36%, compared to the $NAF_2$ algorithm. In addition, we show that $SNAF_w$ algorithm is always faster than $NAF_w$ algorithm, regardless of the size of w.

• Geomechanics and Engineering
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• 제8권4호
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• pp.477-493
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• 2015

In rock drilling, the most important characteristic to clarify is the wear of the drill bits. The reason that the rock drill bits fail with time is wear. In dry sliding contact adhesive wear deteriorates the materials in contact, quickly, and is the result of shear fracture in the momentary contact joins between the surfaces. This paper aims at presenting an overview of the assessment of WC/Co cemented carbide (CC) tricone bit in rotary drilling. To study wear of these bits, two approaches have been used in this research. Firstly, the new bits were weighted before they mounted on the drill rigs and also after completion their useful life to obtain bit weight loss percentage. The characteristics of the rock types drilled by using such this bit were measured, simultaneously. Alternatively, to measure contact wear, namely, matrix wear a micrometer has been used with a resolution of 0.02 mm at different direction on the tricone bits. Equivalent quartz content (EQC), net quartz content (QC), muscovite content (Mu), coarseness index (CI) of drill cuttings and compressive strength of rocks (UCS) were obtained along with thin sections to investigate mineralogical properties in detail. The correlation between effective parameters and bit wear were obtained as result of this study. It was observed that UCS shows no significant correlation with bit wear. By increasing CI and cutting size of rocks wear of bit increases.

• 한국통신학회논문지
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• 제33권10C호
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• pp.798-804
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• 2008

본 논문에서는 마이크로프로세서의 영상 정보 처리 시 L2 캐시의 오류검출 및 정정 회로의 저 전력을 구현하기 위한 오류정정 회로를 제안 하였다. 영상 정보 처리 시에 마이크로프로세서의 L2 캐시에 접근하는 입출력 데이터를 분석하기 위하여 Simplescalar-ARM 사용하여 데이터 입출력에 대한 빈도와 32 bit 처리를 위한 각 bit에 대한 변화율에 대해서 분석한다. 변화량이 많은 비트와 변화량이 적은 비트를 추출하고, 변화의 유사성을 가지는 비트들의 배치를 고려하여 저 전력을 구현할 수 있는 H-matrix를 제안하고 회로를 구현한다. H-spice를 이용하여 구현된 회로와 기존 마이크로프로세서에서 사용하는 Odd-weight-column code의 전력소모에 대한 비교를 위하여 시뮬레이션을 수행하였다. 실험결과 Odd-weight-column code 대비 17%의 소비전력을 감소시킬 수 있었다.

• 정보처리학회논문지B
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• 제11B권4호
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• pp.395-402
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• 2004

본 논문은 비트 플레인별 적응적 임계값을 이용한 대용량 스테가노그라피 방법을 제안하였다. 모든 비트 플레인에 고정적인 임계값을 적용하여 정보를 삽입하면, 비트 플레인에 따라 화질의 열화가 생긴다. 따라서 본 논문에서는 고정 임계값의 문제점을 해결하기 위하여 비트 플레인별 가중치를 정의하였다. 그리고 비트 플레인의 삽입 용량을 적응적으로 증가시키기 위하여, 비트 플레인별 평균 복잡도와 가중치를 이용하여 새로운 적응적 임계값 설정 방법을 제안하였다. 실험에서는 각 표준 이미지에 동일한 화질과 정보량을 삽입하고, 이에 따른 삽입 용량과 화질을 비교하였다. 그 결과, 제안한 방법이 기존의 방법보다 삽입 용량면에서 평균 약 6%의 정도 증가되었고, 화질면에서도 평균 약 2.4dB 향상되었다.

• Journal of Communications and Networks
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• 제7권4호
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• pp.462-470
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• 2005

We propose a multi-rate and multi-BEP transmission scheme using adaptive overlapping pulse-position modulator (OPPM) and optical power controller in optical code division multiple access (CDMA) networks. The proposed system achieves the multi-rate and multi-BEP transmission by accommodating users with different values of OPPM parameter and transmitted power in the same network. The proposed scheme has advantages that the system is not required to change the code length and number of weight depending on the required bit rate of a user and the difference of bit rates does not have so much effect on the bit error probabilities (BEPs). Moreover, the difference of transmitted powers does not cause the change of bit rate. We analyze the BEPs of the four multimedia service classes corresponding to the com­binations of high/low-rates and low/high-BEPs and show that the proposed scheme can easily achieve distinct differentiation of the service classes with the simple system configuration.

• 한방재활의학과학회지
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• 제33권3호
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• pp.1-15
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• 2023

Objectives We aimed to find out the improvement effect of Baekhogainsam-tang (Baihu Jia Renshen-tang, BIT) on metabolic syndrome and alteration of microbiota and gene expression. Methods We used male C57BI/6 mice and randomly assigned them into three groups. Normal control group was fed 10% kcal% fat diet, high-fat diet (HFD) group was fed 45% kcal% fat diet and 10% fructose water. BIT group was fed same diet as HFD group and treated by BIT for once daily, 6 days per week, total 8 weeks. We measured their body weight and food intake every week and performed oral glucose tolerance test 1 week before the end of the study. Then we collected the blood sample to measure triglyceride, total cholesterol, high-density lipoprotein cholesterol, insulin, and hemoglobin A1c. We harvested tissue of liver, muscle, fat, and large intestine for quantitative polymerase chain reaction (qPCR) and histopathological examination. Fresh fecal samples were collected from each animal to verify alterations of gut microbiota and we used RNA from liver tissue for microarray analysis. Results The body weight and fat weight of BIT group were reduced compared to HFD group. The qPCR markers usually up-regulated in metabolic syndrome were decreased in BIT group. Bacteroides were higher in BIT group than other groups. There were also differences in gene expressions between two groups such as Cyp3a11 and Scd1. Conclusions We could find out BIT can ameliorate metabolic syndrome and suggest its effect is related to gut microbiota composition and gene expression pattern.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제5권11호
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• pp.1959-1975
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• 2011

Adaptive Bit Loading (ABL) in Multiple-Input Multiple-Output Orthogonal Frequency-Division Multiplexing (MIMO-OFDM) is often used to achieve the desired Bit Error Rate (BER) performance in wireless systems. In this paper, we discuss some of the bit loading algorithms, compare them in terms of the BER performance, and present an effective and concise Adaptive Grouped Loading (AGL) algorithm. Furthermore, we propose a "weight factor" for loading algorithm to converge rapidly to the final solution for various data rate with variable Signal to Noise Ratio (SNR) gaps. In particular, we consider the bit loading in near optimal Singular Value Decomposition (SVD) based MIMO-OFDM system. While using SVD based system, the system requires perfect Channel State Information (CSI) of channel transfer function at the transmitter. This scenario of SVD based system is taken as an ideal case for the comparison of loading algorithms and to show the actual enhancement achievable by our AGL algorithm. Irrespective of the CSI requirement imposed by the mode of the system itself, ABL demands high level of feedback. Grouped Loading (GL) would reduce the feedback requirement depending upon the group size. However, this also leads to considerable degradation in BER performance. In our AGL algorithm, groups are formed with a number of consecutive sub-channels belonging to the same transmit antenna, with individual gains satisfying predefined criteria. Simulation results show that the proposed "weight factor" leads a loading algorithm to rapid convergence for various data rates with variable SNR gap values and AGL requires much lesser CSI compared to GL for the same BER performance.