• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.73-78
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• 2011

A frequency synthesizer for DAB applications is designed using $0.18{\mu}m$ CMOS process with 1.8V supply. NP-core type is chosen for VCO core to improve low power characteristic and symmetric characteristic of output waveform. VCO range is 1302.34 MHz - 1949.51 MHz using switchable capacitor bank and varactor bank. Varactor biases that improve varactor capacitance characteristics were minimized as two, $K_{vco}$(VCO gain) is maintained using technique of varactor bank switching. Intervals of $K_{vco}$ are maintained adding VCO frequency compensation logic. Each block of VCO and frequency synthesizer designed $0.18{\mu}m$ CMOS process with 1.8V supply is verified by Cadence Spectre, measured VCO consumes 9mA current, and is 39.8% tuning range, total power consumption of the frequency synthesizer is 18mW.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.34 no.8
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• pp.104-108
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• 2006

There are range and azimuth direction resolution of synthetic aperture radar on the aircraft or satellite. Wide bandwidth chirp pulse generation technology is prerequisite for SAR image with fine resolution. There are two kinds of digital chirp pulse generation technology as arbitrary waveform generator(AWG) and direct digital synthesizer(DDS). In this paper, we design and implement a digital chirp pulse generator to generate 300MHz wide bandwidth linear FM chirp pulse for the fine resolution image with direct digital synthesizer. Implemented chirp pulse generator can be useful for the SAR sensors to make 50cm range resolution image.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.475-476
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• 2007

Electroglottography (EGG) is a technique used to register laryngeal behavior indirectly by a measuring the change in electrical impedance across the throat during speaking. However, EGG waveform is affected by laryngeal muscles which fluctuate the vocal cords, and which result in baseline wander. It is required to reduce baseline wander in EGG waveform, because EGG waveform is used for input signal of nonlinear speech synthesizer in next chapter. In vocal cords, the abduction-adduction of glottis is mainly controlled by the posterior cricoarytenoid (abductor) and interarytenoid (adductor) muscles respectively. Empirical Mode Decomposition method was adopted in cancellation of EGG waveform baseline wandering, and showd better performance than that of high pass filter with 500 order.

• The Bulletin of The Korean Astronomical Society
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• v.37 no.2
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• pp.228.1-228.1
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• 2012

Digital waveform generation technology for SAR payload can be divided into DDS(Direct Digital Synthesizer) method and Memory Mapped(M/M) method. DDS is the single chip which consists of the Sine Table, NCO(Numerically Controlled Oscillator), DAC, and so on. DDS method is a very simple method because the circuit configuration is not complex but has a disadvantage that can not control phase and amplitude easily by using NCO. M/M method has the complexity of the circuit configuration because it requires the memories which stores the waveforms, the control circuits, and DAC. And this method should apply the high interface technology for being compatible with the wide bandwidth of the digital signal and has the difficulty for PCB design because the number of the signal lines should be increased according to the number of the data bits for DAC. Although it has several disadvantages, this method has the capability of pre-distortion function which can compensate the phase and amplitude characteristics of the system and also has an excellent advantage to make any arbitrary waveform, so this method is considered as an important technology with DDS method. This research describes the technological trends of the waveform generator for the SAR payload and analyzes the characteristics of the technology.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.951-954
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• 1999

A direct digital frequency synthesizer is designed in full custom method using 0.65${\mu}{\textrm}{m}$ CMOS n-well technology The chip provides the capability of the parallel operation using up to 4 chips with an operation frequency of 440MHz. The generated waveform can be modulated by various modulation techniques such as QPSK, 256 . 64. 32 . 16 QAM and FM.

• The Journal of the Acoustical Society of Korea
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• v.18 no.5
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• pp.52-57
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• 1999

It is very important to design of QAM modulator of high spectral efficiency for high speed data transmission. In this paper, typical 16-QAM modulator is designed by modification design of DDFS(direct digital frequency synthesizer). DDFS generates sinusoidal waveform digitally to the frequency setting word. Phase modulation is accuratly made by control of a generated phase increment value and amplitude modulation is accomplished in the D/A converter output by control of amplitude level. For the suppression of harmonics and glitch, dual-structured DDFS is studied to improve the spurious characteristics. P-Spice is used for design and simulation in mixed mode. Also we can get the satisfactory results of designed 16-QAM modulator from the constellation output.

• Journal of the Korean Magnetics Society
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• v.7 no.6
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• pp.327-333
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• 1997

We designed and constructed the high frequency magnetic characteristics measurement system to measure core loss, B-H curve, permeability of toroidal ferrite core, amorphous core and various materials for high frequency application. The system consists of universal equipments such as digitizing oscilloscope, signal generator, power amplifier, PC in order to make upgrade easily. The power source is composed of waveform synthesizer and power amplifier ranging from DC to 20 MHz, and output signal H and B from sample core are digitized by oscilloscope with sampling rate 1 GS/ s per channel. Computer controls power source and oscilloscope, reads data from oscilloscope, displays analyzed waveform and saves data with file. The entire procedures finishes within few seconds.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.2064-2071
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• 1998

A new digital clock level translator has been designed in order to produce a clock source of the internal logic circuits. The translator output has 50% duty ratio from small sinusoidal input such as TCXO which oscillates itself in poratable components. The circuit consists of positive and negative comparators, RS latch, charge pump, and reference vol- tage generator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator reference, producing output waveform with valid 50% duty ratio of the digital signal level. The designed level translator can be used as a sampling clock source of ADC, PLL and the colck source of the clock synthesizer. The circuit wasdesigned in a 0.8.mu.m analog CMOS technology with double metal, double poly, and BSIM3 circuit simulation model. From our experimental results, a stable operating characteristics of 50 +3% duty ratio was obtained from the sinusoidal input wave of 370 mV.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.6
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• pp.591-597
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• 1988

In this paper, we have studied a channel capacity affected by noise which produces burst errors in the ISDN(approx 140Kbps) data transmission using a existing PSTN. First, a digital communication system model to apply a subscriber line to a narrow band ISDN channel is presented. Second, the decision methodology of a channel capacity limitation whether the pdf of the noise generated by a waveform synthesizer is Pisson or Laplacian is described. As a result of the simulation, we have obtained that the Poission distributed noise is approached to the Guassian rather than the Laplacian under the same SNR condition.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.10
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• pp.914-924
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• 1991

It has been generally used for PLL(Phase Locked Loop) to be synthesized randomly chosen frequency state, but the PLL locking time was inevitable element. A direct digital synthesizer. Which makes output frequency directly in sine wave by a phase accumulating method, could be leiminate the defect, although a phase distortion in frequency spectrum. In order to improve this disadvantage, the phase accumulating method is reconsidered in the side of he output wave formula expression. A new mechanism is proposed, and it is constructed by a most suitable logic elements. The spectrum of synthesized sine waveform is simulated and compared with a measured value, and it’s the coherence frequency hoppong state with the PN(Pseudo Noise) code sequence is confirmed. In this results, the power levels of phase distortion harmonics are decreased to 10~25dB and bandwidths are increased to 420kHz.