• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2012년도 춘계학술대회 논문집
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• pp.807-808
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• 2012

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1997년도 춘계학술대회 논문집
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• pp.921-926
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• 1997

SOI(Silicon On lnsulator) technology is many advantages in the gabrication of MOS(Metal-Oxide Semiconductor) and CMOS(Complementary MOS) structures. These include high speed, lower dynamic power consumption,greater packing density, increased radiation tolearence et al. In smiple form of bonded SOL wafer manufacturing, creation of a bonded SOI structure involves oxidizing at least one of the mirror polished silicon surfaces, cleaning the oxidized surface and the surface of the layer to which it will be bonded,bringing the two cleanded surfaces together in close physical proximity, allowing the subsequent room temperature bonding to proceed to completion, and than following this room temperature joining with some form of heat treatment step,and device wafer is thinned to the target thickness. This paper has been performed to investigate the possibility of the bonded SOI wafer manufacturing Especially, we focused on the bonding quality and thinning method. Finally,we achieved the bonded SOI wafer that Si layer thickness is below 3 .mu. m and average roughness is below 5.angs.

• 전기학회논문지
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• 제60권7호
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• pp.1434-1437
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• 2011

Precision measurement of silicon wafer resistivity has been using single-configuration Four-Point Probe(FPP) method. This FPP method have to applying sample size, shape and thickness correction factor for a probe pin spacing to precision measurement of silicon wafer. The deference for resistivity measurement values applied correction factor and not applied correction factor was about 1.0 % deviation. The sample size, shape and thickness correction factor for a probe pin spacing have an effects on precision measurement for resistivity of silicon wafer.

• 대한기계학회논문집A
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• 제29권9호
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• pp.1169-1174
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• 2005

Imprint lithography is a promising method for high-resolution and high-throughput lithography using low-cost equipment. In particular, ultraviolet-nanoimprint lithography (UV-NIL) is applicable to large area imprint easily. We have proposed a new UV-NIL process using an elementwise patterned stamp (EPS), which consists of a number of elements, each of which is separated by channel. Experiments on UV-NIL are performed on an EVG620-NIL using the EPS with 3mm channel width. The replication of uniform sub 70 nm lines using the EPS is demonstrated. We investigate the nonuniformity of residual layer caused by wafer deformation in experiment with varying wafer thickness. Severely deformed wafer works as an obstacle in spreading of dropped resin, which causes nonuniformity of thickness of residual layer. Numerical simulations are conducted to analyze aforementioned phenomenon. Wafer deformation in the process is simulated by using a simplified model, which is a good agreement with experiments.

• 반도체디스플레이기술학회지
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• 제22권3호
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• pp.8-13
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• 2023

High bandwidth memory a core technology of the future memory semiconductor industry, is attracting attention. Temporary bonding and debonding process technology, which plays an important role in high bandwidth memory process technology, is also being studied. In this process, total thickness variation is a major factor determining wafer performance. In this study, the reliability of the equipment measuring total thickness variation is identified, and the servo motor settling, and wafer total thickness variation measurement accuracy are analyzed. As for the experimental variables, vacuum, acceleration time, and speed are changed to find the most efficient value by comparing the stabilization time. The smaller the vacuum and the larger the radius, the longer the settling time. If the radius is small, high-speed rotation performance is good, and if the radius is large, low-speed rotation performance is good. In the future, we plan to conduct an experiment to measure the entire of the wafer.

• 센서학회지
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• 제16권5호
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• pp.325-330
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• 2007

For the application to optic devices, wafer level package including spacer with particular thickness according to optical design could be required. In these cases, the uniformity of spacer thickness is important for bonding strength and optical performance. Packaging process has to be performed at low temperature in order to prevent damage to devices fabricated before packaging. And if photosensitive material is used as spacer layer, size and shape of pattern and thickness of spacer can be easily controlled. This paper presents polymer bonding using thick, uniform and patterned spacing layer of SU-8 2100 photoresist for wafer level package. SU-8, negative photoresist, can be coated uniformly by spin coater and it is cured at $95^{\circ}C$ and bonded well near the temperature. It can be bonded to silicon well, patterned with high aspect ratio and easy to form thick layer due to its high viscosity. It is also mechanically strong, chemically resistive and thermally stable. But adhesion of SU-8 to glass is poor, and in the case of forming thick layer, SU-8 layer leans from the perpendicular due to imbalance to gravity. To solve leaning problem, the wafer rotating system was introduced. Imbalance to gravity of thick layer was cancelled out through rotating wafer during curing time. And depositing additional layer of gold onto glass could improve adhesion strength of SU-8 to glass. Conclusively, we established the coating condition for forming patterned SU-8 layer with $400{\mu}m$ of thickness and 3.25 % of uniformity through single coating. Also we improved tensile strength from hundreds kPa to maximum 9.43 MPa through depositing gold layer onto glass substrate.

• 마이크로전자및패키징학회지
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• 제30권3호
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• pp.88-93
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• 2023

고대역폭 메모리(HBM)에 대한 수요가 증가하고 직경이 더 큰 웨이퍼의 핸들링 기술이 발전함에 따라 본딩 웨이퍼의 두께 균일성에 대해 신뢰성을 확보할 수 있는 측정 방법이 요구되고 있다. 본 연구에서는 300mm 웨이퍼를 대상으로 웨이퍼의 전 영역에 대해 TTV를 측정할 수 있는 모듈을 설계 제직하고, 측정 모듈의 설계를 바탕으로 발생할 수 있는 측정 오차를 분석하였으며, 웨이퍼의 처짐과 척의 기구적 오차를 고려한 모델 해석을 통해 예측된 기울기 값에 따른 측정 오차를 추정하였다. TTV 측정 모듈은 웨이퍼 지지를 위한 센터 척과 리프트 핀을 활용하여 웨이퍼의 전체 영역에 대해 측정이 가능하도록 하였다. 모달 해석을 통해 모듈의 구조적 안정성을 예측하였으며, 구동부와 측정부 모두 100Hz 이상의 강성을 갖는 것을 확인하였다. 설계된 모듈의 측정 오차를 예측한 결과 두께 1,500um의 본딩 웨이퍼를 측정할 경우 예측된 측정 오차는 1.34nm로 나타났다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.86-87
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• 2007

The dispersive method of white-light interferometry is proper for in-line 3-D inspection of dielectric thin-film thickness to be used in the semiconductor and flat-panel display industry. This research is the measurement application of CMP patterned wafer. The results describe 3-D and 2-D profile of the step height during polishing time.

• Transactions on Electrical and Electronic Materials
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• 제3권4호
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• pp.5-9
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• 2002

Chemical mechanical polishing (CMP) has become the preferred planarization method for multilevel interconnect technology due to its ability to achieve a high degree of feature level planarity. Especially, to achieve the higher density and greater performance, shallow trench isolation (STI)-CMP process has been attracted attention for multilevel interconnection as an essential isolation technology. Also, it was possible to apply the direct STI-CMP process without reverse moat etch step using high selectivity slurry (HSS). In this work, we determined the process margin with optimized process conditions to apply HSS STI-CMP process. Then, we evaluated the reliability and reproducibility of STI-CMP process through the optimal process conditions. The wafer-to-wafer thickness variation and day-by-day reproducibility of STI-CMP process after repeatable tests were investigated. Our experimental results show, quite acceptable and reproducible CMP results with a wafer-to-wafer thickness variation within 400$\AA$.

• 디지털콘텐츠학회 논문지
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• 제5권4호
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• pp.251-256
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• 2004

반도체 집적회로를 만드는 토대가 되는 실리콘 웨이퍼의 표면은 고품질 회로를 구성하기 위해 극도의 평탄도가 요구되므로 평탄도는 양질의 웨이퍼를 보증하는 가장 중요한 요소이다. 따라서 실리콘웨이퍼 생산의 10개의 공정 중 거칠어진 웨이퍼 표면을 고도의 평탄도를 갖도록 연마하는 폴리싱공정은 매우 중요시 되는 생산라인이다. 현재 이 공정에서는 담당 엔지니어가 웨이퍼의 모형을 측정장비의 모니터에서 육안으로 관찰하여 판단하고 평탄도를 높이기 위한 제어를 하고 있다. 그러나 사람에 의한 것이므로 많은 경험이 필요하고 일일이 체크해야하는 번거로움이 있다. 본 연구는 이러한 비효율적인 작업의 효율화를 위해 웨이퍼의 모형을 디지털 컨텐츠화하여 폴리싱 공정에 있어 평탄도를 사람이 아닌 시스템에 의해 자동으로 측정하여 제어하는 알고리즘을 제안한다. 또한 제안한 전체 웨이퍼 평탄도 추정알고리즘을 토대로 실제 현장에서 쓰이는 웨이퍼 각 사이트별 평탄도를 측정하기 위한 사이트두께 추정 알고리즘을 제안한다.