• Transactions of the Korean Society of Mechanical Engineers B
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• v.26 no.4
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• pp.524-530
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• 2002

Micro electric spark discharge device was fabricated on a FOTURAN glass wafer using MEMS processing technique and its performance of electron discharge and subsequent formation of ignition kernel were tested. Micro electric spark device is an essential subsystem of a power MEMS that has been under development in this laboratories. In a combustion chamber of sub millimeter scale depth, spark electrodes are formed by electroplating Ni on a base plate of FOTURAN glass wafer. Optimization of spark voltage and spark gap is crucial for stable ignition and endurance of the electrodes. Namely, wider spark gaps insures stable ignition but requires higher ignition voltage to overcome the spark barrier. Also, electron discharge across larger voltage tends to erode the electrodes limiting the endurance of the overall system. In the present study, the discharge characteristics of the proptotype ignition device was measured in terms of electric quantities such as voltage and currant with spark gap and end shape as parameters. Discharge voltage shows a little decrease in width of less than 50㎛ and increases with electrode gap size. Reliability test shows no severe damage over 10$\^$6/ times of discharge test resulting in satisfactory performance for application to proposed power MEMS devices.

• Korean Journal of Materials Research
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• v.24 no.8
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• pp.429-433
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• 2014

As the fabrication technology used in FPDs(flat-panel displays) advances, the size of these panels is increasing and the pattern size is decreasing to the um range. Accordingly, a cleaning process during the FPD fabrication process is becoming more important to prevent yield reductions. The purpose of this study is to develop a FPD cleaning system and a cleaning process using a two-phase flow. The FPD cleaning system consists of two parts, one being a cleaning part which includes a two-phase flow nozzle, and the other being a drying part which includes an air-knife and a halogen lamp. To evaluate the particle removal efficiency by means of two-phase flow cleaning, silica particles $1.5{\mu}m$ in size were contaminated onto a six-inch silicon wafer and a four-inch glass wafer. We conducted cleaning processes under various conditions, i.e., DI water and nitrogen gas at different pressures, using a two-phase-flow nozzle with a gap distance between the nozzle and the substrate. The drying efficiency was also tested using the air-knife with a change in the gap distance between the air-knife and the substrate to remove the DI water which remained on the substrate after the two-phase-flow cleaning process. We obtained high efficiency in terms of particle removal as well as good drying efficiency through the optimized conditions of the two-phase-flow cleaning and air-knife processes.

• Korean Chemical Engineering Research
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• v.53 no.3
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• pp.401-406
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• 2015

Getter is a class of materials used in absorbing gases such as hydrogen and moisture in microelectronics or semiconductor devices to operate properly. In this study, we developed a new device structure consisting of porous anodized alumina films on textured silicon wafer, which have cost efficiency in materials and processing aspects. Anodic aluminum oxide (AAO) with controlled pore sizes can be applied to a high-efficiency moisture absorber due to the high surface area and OH- saturated surface property. The moisture sorption capacity was 2.02% (RH=35%), obtained by analyzing isothermal adsorption/desorption curve.

• Korean Journal of Materials Research
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• v.4 no.5
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• pp.510-515
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• 1994

Yttria-stabilized zirconia(YSZ) films were prepared onto p-type (100) silicon wafer by a plasma-enhanced metallorganic chemical vapor deposition(PE MO CVD) processing involving the application of vapor mixture of tri(2.2.6.6-tetramethyl-3, 5-heptanate) yttrium$[Y(DPM)_3]$, zirconiumtriflouracethyla cetonate$(Zr(tfacac)_4$ and oxygen gas. The x-ray diffraction(XRD) and fourier transform infrared spectra(FT1R) results showed that the deposited YSZ films had a single cubic phase. $Y_2O_3$ content of YSZ film was analyzed by PIXE(partic1e induced x-ray emission). The experimental results by PIXE revealed that 12.lmol%, 20.4mol% and 31.6mol% $Y_2O_3$ could be obtained as the $Y(DPM)_3$ bubbling temperature varied at $160^{\circ}C, 165^{\circ}C$ and $170^{\circ}C$ respectively. The increase of $Y(DPM)_3$ bubbling temperature caused shifting flat band voltage to have a negative value.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.38 no.4
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• pp.159-167
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• 2015

We consider a wafer lot transfer/release planning problem from semiconductor wafer fabrication facilities to probing facilities with the objective of minimizing the deviation of workload and total tardiness of customers' orders. Due to the complexity of the considered problem, we propose a two-level hierarchical production planning method for the lot transfer problem between two parallel facilities to obtain an executable production plan and schedule. In the higher level, the solution for the reduced mathematical model with Lagrangian relaxation method can be regarded as a coarse good lot transfer/release plan with daily time bucket, and discrete-event simulation is performed to obtain detailed lot processing schedules at the machines with a priority-rule-based scheduling method and the lot transfer/release plan is evaluated in the lower level. To evaluate the performance of the suggested planning method, we provide computational tests on the problems obtained from a set of real data and additional test scenarios in which the several levels of variations are added in the customers' demands. Results of computational tests showed that the proposed lot transfer/planning architecture generates executable plans within acceptable computational time in the real factories and the total tardiness of orders can be reduced more effectively by using more sophisticated lot transfer methods, such as considering the due date and ready times of lots associated the same order with the mathematical formulation. The proposed method may be implemented for the problem of job assignment in back-end process such as the assignment of chips to be tested from assembly facilities to final test facilities. Also, the proposed method can be improved by considering the sequence dependent setup in the probing facilities.

• Journal of the Semiconductor & Display Technology
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• v.20 no.2
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• pp.92-97
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• 2021

The importance of processes in cryogenic environments is increasing in a way to address problems such as critical dimension (CD) narrow and bottlenecks in micro-processing. Accordingly, in this paper, we proceed with the design and analysis of Electrostatic Chuck(ESC) and Coolant in cryogenic environments, and present optimal model conditions to provide the temperature distribution analysis of ESC in these environments and the appropriate optimal design. The wafer temperature uniformity was selected as the reference model that the operating conditions of the refrigerant of the liquid nitrogen in the doubled aluminum path were excellent. Design of simulation (DOS) was carried out based on the wheel settings within the selected reference model and the classification of three mass flow and diameter case, respectively. The comparison between factors with p-value less than 0.05 indicates that the optimal design point is when five turns of coolant have a flow rate of 0.3 kg/s and a diameter of 12 mm. ANOVA determines the interactions between the above factor, indicating that mass flow is the most significant among the parameters of interests. In variable selection procedure, Case 2 was also determined to be superior through the two-Sample T-Test of the mean and variance values by dividing five coolant wheels into two (Case 1 : 2+3, Case 2: 3+2). Finally, heat transfer analysis processes such as final difference method (FDM) and heat transfer were also performed to demonstrate the feasibility and adequacy of the analysis process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.4
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• pp.332-340
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• 2023

Crystalline silicon solar cells have attracted great attention for their various advantages, such as the availability of raw materials, high-efficiency potential, and well-established processing sequence. Tunnel oxide passivated contact (TOPCon) solar cells are widely regarded as one of the most prospective candidates for the next generation of high-performance solar cells because an efficiency of 26% has been achieved in small-area solar cells. Compared to n-type TOPCon solar cells, the photo conversion efficiency (PCE) of p-type TOPCon is slightly higher. The highest PCEs of p-type TOPCon and n-type TOPCon solar cells are 26.0% and 25.8%, respectively. Despite the highest efficiency in small-area cells, limited progress has been achieved in p-type TOPCon solar cells for large are due to their lower carrier lifetime and inferior surface passivation with the boron-doped c-Si wafer. Nevertheless, it is of great importance to promoting the p-type TOPCon technology due to its lower price and well-established manufacturing procedures with slight modifications in the PERC solar cells production lines. The progress in different approaches to increase the efficiencies of p-type TOPCon solar cells has been reported in this review article and is expected to set valuable strategies to promote the passivation technology of p-type TOPCon, which could further increase the efficiency of TOPCon solar cells.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.3
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• pp.108-115
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• 1990

This paper describes the design and fabrication of a processing element that will be used as a component in the construction of a two dimensional systolic for FFT. The chip performs data shuffling and radix-2 decimation-in-time (DIT) butterfly arithmetic. It consists of a data routing unit, internal control logic and HBA unit which computes butterfly arithmetic. The 6.5K transistors processing element designed with standard cells has been fabricated with a 2u'm double metal CMOS process, and evaluated by wafer probing measurements. The measured characteristics show that a HBA can be computed in 0.5 usec with a 20MHz clok, and it is estimated that the FFT of length 1024 can be transformed in 11.2 usec.

• ETRI Journal
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• v.25 no.6
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• pp.503-509
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• 2003

Selective epitaxial growth (SEG) of silicon has attracted considerable attention for its good electrical properties and advantages in building microstructures in high-density devices. However, SEG problems, such as an unclear process window, selectivity loss, and nonuniformity have often made application difficult. In our study, we derived processing diagrams for SEG from thermodynamics on gas-phase reactions so that we could predict the SEG process zone for low pressure chemical vapor deposition. In addition, with the help of both the concept of the effective supersaturation ratio and three kinds of E-beam patterns, we evaluated and controlled selectivity loss and non-uniformity in SEG, which is affected by the loading effect. To optimize the SEG process, we propose two practical methods: One deals with cleaning the wafer, and the other involves inserting dummy active patterns into the wide insulator to prevent the silicon from nucleating.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.5-6
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• 2009

In this paper, plasma ion implant is performed with $PH_3$ gas diluted by helium gas on P-type Si wafer (100). Spike Rapid Thermal Processing(RTP) annealing performed for 30~60 sec from $800\;^{\circ}C$ to $1000\;^{\circ}C$ in $N_2+O_2$ ambient. Crystalline defect is analyzed by Transmission Electron Microscope(TEM) and Double crystal X-ray Diffraction(DXRD). Contact resistivity($\rho c$), contact resistance(Rc) and sheet resistance(Rs) are analyzed by measuring Transfer Length Method(TLM) using 4155C analysis. As annealing temperature increase, Rs decrease and ${\rho}c$ and Rc increase at temperature higher than $850\;^{\circ}C$. We achieve low Rs, ${\rho}c$ and Rc with Plasma ion implant and spike RTP.