• 반도체디스플레이기술학회지
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• 제20권2호
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• pp.19-24
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• 2021

As the size of semiconductor devices decreases, the etching pattern becomes very narrow and a deep high aspect ratio process becomes important. The cryogenic etching process enables high aspect ratio etching by suppressing the chemical reaction of reactive ions on the sidewall while maintaining the process temperature of -100℃. ESC is an important part for temperature control in cryogenic etching equipment. Through the cooling path inside the ESC, liquid nitrogen is used as cooling water to create a cryogenic environment. And since the ESC directly contacts the wafer, it affects the temperature uniformity of the wafer. The temperature uniformity of the wafer is closely related to the yield. In this study, the cooling path was designed and analyzed so that the wafer could have a uniform temperature distribution. The optimal cooling path conditions were obtained through the analysis of the shape of the cooling path and the change in the speed of the coolant. Through this study, by designing ESC with optimal temperature uniformity, it can be expected to maximize wafer yield in mass production and further contribute to miniaturization and high performance of semiconductor devices.

• 반도체디스플레이기술학회지
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• 제17권4호
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• pp.86-90
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• 2018

Standards related to express the non-flatness of a wafer are reviewed and discussed, for example, bow, warp, and sori. Novel wafer warpage measurement method is proposed for 3D stacked IC application. The new way measures heat transfer from a heater to a wafer, which is a function of the contact area between these two surfaces and in turn, this contact area depends on the wafer warpage. Measurement options such as heating from room temperature and cooling from high temperature were experimentally examined. The heating method was found to be sensitive to environmental conditions. The cooling technique showed more robust and repeatable results and the further investigation for the optimal cooling condition is underway.

• 전자공학회논문지A
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• 제31A권2호
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• pp.81-87
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• 1994

We used IR laser inteferometric technique for measuring the temperature of wafer during cryogenic ECR etching. Using this technique, the effect of RF bias power and microwave power on the wafer temperature during etching period is investigated. As the RF bias power and microwave power was increased, the temperature of the wafer considerably increased and we concluded that to prevent the increase of substrate temperature during etching period, an adequate wafer cooling is needed.

• 반도체디스플레이기술학회지
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• 제17권3호
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• pp.85-89
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• 2018

Temperature uniformity of a wafer in a semiconductor process is a very important factor that determines the overall yield. Therefore, it is very important to confirm the temperature characteristics of the chuck surface on which the wafer is lifted. The temperature characteristics of the chuck depend on the external heat source, the shape of the cooling channel inside the chuck, the material on the chuck surface, and so on. In this study, CFD confirms the change of temperature characteristics according to the stacking order of ceramic materials and inner coolant path on the chuck surface. Finally this study suggests the best cooling condition of electrostatic chuck.

• 반도체디스플레이기술학회지
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• 제17권3호
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• pp.100-103
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• 2018

Due to the plasma applied from the outside, which acts as an etchant during the etching process, considerable heat is transferred to the wafer and a separate cooling process is performed to effectively remove the heat after the process. In this case, a direct cooling method using a refrigerant is suitable for cooling through effective heat exchange. The direct cooling method using the refrigerant using the latent heat exchange is superior to the cooling method using the sensible heat exchange. Therefore, in this paper, AMESim is used to design a direct refrigerant cooling system using latent heat exchange simulator was built.The constructed simulator is reliable compared with the actual experimental results. It is expected that this simulator will help to design and search for optimal process conditions.

• 반도체디스플레이기술학회지
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• 제16권3호
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• pp.106-110
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• 2017

Due to the plasma applied from the outside, which acts as an etchant during the etching process, considerable heat is transferred to the wafer and a separate cooling process is performed to effectively remove the heat after the process. In this case, a direct cooling method using a refrigerant is suitable for cooling through effective heat exchange. The direct cooling method using the refrigerant using the latent heat exchange is superior to the cooling method using the sensible heat exchange. Therefore, in this paper, AMESim is used to design a direct refrigerant cooling system using latent heat exchange simulator was built.The constructed simulator is reliable compared with the actual experimental results. It is expected that this simulator will help to design and search for optimal process conditions.

• 마이크로전자및패키징학회지
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• 제23권2호
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• pp.73-78
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• 2016

집적회로(Integrated Circuit) 소자의 트랜지스터(transistor) 밀도 증가는 소자에서 발생하는 열 방출(heat dissipation)의 급격한 상승을 초래하여 열 문제를 발생시키고, 이는 소자의 성능과 열적 신뢰성에 영향을 크게 미친다. 열문제의 해결방안 중 본 연구에서는 냉매를 이용한 액체 냉각방법을 연구하였으며, 실리콘 웨이퍼에 관통실리콘비아(through Si via)와 마이크로 채널(microchannel)을 딥 반응성 이온 애칭(deep reactive ion etching)로 구현한 후 유리기판과 어노딕본딩을 통하여 액체 냉각 구조를 제작하였다. 제작된 마이크로 채널 위에 Ag, Cu 또는 Cr/Au/Cu bump를 스크린프린팅(screen printing) 방법으로 형성하였고, 범프의 유무를 통해 액체 냉각 전후의 냉각 모듈의 실리콘 표면온도의 변화를 적외선현미경으로 분석하였다. Cr/Au/Cu bump가 탑재된 액체 냉각 모듈의 경우 가열온도 $200^{\circ}C$에서 냉각 전후의 실리콘 표면 온도 차이는 약 $45.2^{\circ}C$이고, 전력밀도 감소는 약 $2.8W/cm^2$ 이었다.

• 수산해양교육연구
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• 제19권3호
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• pp.366-372
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• 2007

This paper presents the fabrication techniques of microcooling fins for microelectronics applications. The various types of cooling fins have been fabricated on the surface of a silicon wafer (4inch-N type) by using wet etching technique. The designed micro fins and micro channels are considered as an effective method for cooling microelectronics devices generating high heat flux. Further we extensively investigate the design processes fabricating micro fins and channels which can cool the heat generated from high density electronics devices.

• 동력기계공학회지
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• 제5권2호
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• pp.36-42
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• 2001

This paper deals with finite element analyses of residual stresses causing popping up which are induced in micromachining processes of a microaccelerometer sensors. The paddle of the micro accelerometer sensor is designed symmetric with respect to the direction of the beam. After heating the tunnel gap up to 100 degree and get it through the cooling process and the additional beam up to 80 degree and get it through the cooling process. We learn the thermal internal stresses of each shape and compare the results with each other, after heating the tunnel gap up to 400 degree during the Pt deposition process. Finally we find the optimal shape which is able to minimize the internal stresses of microaccelerometer sensor. We want to seek after the real cause of this pop up phenomenon and diminish this by change manufacturing processes of microaccelerometer sensor by electrostatic force.

• 한국정밀공학회지
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• 제27권2호
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• pp.13-19
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• 2010

Due to the rapid spread of mobile handheld devices, industrial demands for micro-scale holes with a diameter of even smaller than $10{\mu}m$ in sapphire/silicon wafers have been increasing. Holes in sapphire wafers are for heat dissipation from LEDs; and those in silicon wafers for interlayer communication in three-dimensional integrated circuit (IC). We have developed a sapphire wafer driller equipped with a 532nm laser in which a cooling chuck is employed to minimize local heat accumulation in wafer. Through the optimization of process parameters (pulse energy, repetition rate, number of pulses), quality holes with a diameter of $30{\mu}m$ and a depth of $100{\mu}m$ can be drilled at a rate of 30holes/sec. We also have developed a silicon wafer driller equipped with a 355nm laser. It is able to drill quality through-holes of $15{\mu}m$ in diameter and $150{\mu}m$ in depth at a rate of 100holes/sec.