• Journal of the Semiconductor & Display Technology
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• v.20 no.2
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• pp.19-24
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• 2021

As the size of semiconductor devices decreases, the etching pattern becomes very narrow and a deep high aspect ratio process becomes important. The cryogenic etching process enables high aspect ratio etching by suppressing the chemical reaction of reactive ions on the sidewall while maintaining the process temperature of -100℃. ESC is an important part for temperature control in cryogenic etching equipment. Through the cooling path inside the ESC, liquid nitrogen is used as cooling water to create a cryogenic environment. And since the ESC directly contacts the wafer, it affects the temperature uniformity of the wafer. The temperature uniformity of the wafer is closely related to the yield. In this study, the cooling path was designed and analyzed so that the wafer could have a uniform temperature distribution. The optimal cooling path conditions were obtained through the analysis of the shape of the cooling path and the change in the speed of the coolant. Through this study, by designing ESC with optimal temperature uniformity, it can be expected to maximize wafer yield in mass production and further contribute to miniaturization and high performance of semiconductor devices.

• Journal of the Semiconductor & Display Technology
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• v.17 no.4
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• pp.86-90
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• 2018

Standards related to express the non-flatness of a wafer are reviewed and discussed, for example, bow, warp, and sori. Novel wafer warpage measurement method is proposed for 3D stacked IC application. The new way measures heat transfer from a heater to a wafer, which is a function of the contact area between these two surfaces and in turn, this contact area depends on the wafer warpage. Measurement options such as heating from room temperature and cooling from high temperature were experimentally examined. The heating method was found to be sensitive to environmental conditions. The cooling technique showed more robust and repeatable results and the further investigation for the optimal cooling condition is underway.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.2
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• pp.81-87
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• 1994

We used IR laser inteferometric technique for measuring the temperature of wafer during cryogenic ECR etching. Using this technique, the effect of RF bias power and microwave power on the wafer temperature during etching period is investigated. As the RF bias power and microwave power was increased, the temperature of the wafer considerably increased and we concluded that to prevent the increase of substrate temperature during etching period, an adequate wafer cooling is needed.

• Journal of the Semiconductor & Display Technology
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• v.17 no.3
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• pp.85-89
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• 2018

Temperature uniformity of a wafer in a semiconductor process is a very important factor that determines the overall yield. Therefore, it is very important to confirm the temperature characteristics of the chuck surface on which the wafer is lifted. The temperature characteristics of the chuck depend on the external heat source, the shape of the cooling channel inside the chuck, the material on the chuck surface, and so on. In this study, CFD confirms the change of temperature characteristics according to the stacking order of ceramic materials and inner coolant path on the chuck surface. Finally this study suggests the best cooling condition of electrostatic chuck.

• Journal of the Semiconductor & Display Technology
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• v.17 no.3
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• pp.100-103
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• 2018

Due to the plasma applied from the outside, which acts as an etchant during the etching process, considerable heat is transferred to the wafer and a separate cooling process is performed to effectively remove the heat after the process. In this case, a direct cooling method using a refrigerant is suitable for cooling through effective heat exchange. The direct cooling method using the refrigerant using the latent heat exchange is superior to the cooling method using the sensible heat exchange. Therefore, in this paper, AMESim is used to design a direct refrigerant cooling system using latent heat exchange simulator was built.The constructed simulator is reliable compared with the actual experimental results. It is expected that this simulator will help to design and search for optimal process conditions.

• Journal of the Semiconductor & Display Technology
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• v.16 no.3
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• pp.106-110
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• 2017

Due to the plasma applied from the outside, which acts as an etchant during the etching process, considerable heat is transferred to the wafer and a separate cooling process is performed to effectively remove the heat after the process. In this case, a direct cooling method using a refrigerant is suitable for cooling through effective heat exchange. The direct cooling method using the refrigerant using the latent heat exchange is superior to the cooling method using the sensible heat exchange. Therefore, in this paper, AMESim is used to design a direct refrigerant cooling system using latent heat exchange simulator was built.The constructed simulator is reliable compared with the actual experimental results. It is expected that this simulator will help to design and search for optimal process conditions.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.2
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• pp.73-78
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• 2016

An increase in the transistor density of integrated circuit devices leads to a very high increase in heat dissipation density, which causes a long-term reliability and various thermal problems in microelectronics. In this study, liquid cooling method was investigated using straight microchannels with various metal bumps. Microchannels were fabricated on Si wafer using deep reactive ion etching (DRIE), and Ag, Cu, or Cr/Au/Cu metal bumps were placed on Si wafer by a screen printing method. The surface temperature of liquid cooling structures with various metal bumps was measured by infrared (IR) microscopy. For liquid cooling with Cr/Au/Cu bumps, the surface temperature difference before and after liquid cooling was $45.2^{\circ}C$ and the power density drop was $2.8W/cm^2$ at $200^{\circ}C$ heating temperature.

• Journal of Fisheries and Marine Sciences Education
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• v.19 no.3
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• pp.366-372
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• 2007

This paper presents the fabrication techniques of microcooling fins for microelectronics applications. The various types of cooling fins have been fabricated on the surface of a silicon wafer (4inch-N type) by using wet etching technique. The designed micro fins and micro channels are considered as an effective method for cooling microelectronics devices generating high heat flux. Further we extensively investigate the design processes fabricating micro fins and channels which can cool the heat generated from high density electronics devices.

• Journal of Power System Engineering
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• v.5 no.2
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• pp.36-42
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• 2001

This paper deals with finite element analyses of residual stresses causing popping up which are induced in micromachining processes of a microaccelerometer sensors. The paddle of the micro accelerometer sensor is designed symmetric with respect to the direction of the beam. After heating the tunnel gap up to 100 degree and get it through the cooling process and the additional beam up to 80 degree and get it through the cooling process. We learn the thermal internal stresses of each shape and compare the results with each other, after heating the tunnel gap up to 400 degree during the Pt deposition process. Finally we find the optimal shape which is able to minimize the internal stresses of microaccelerometer sensor. We want to seek after the real cause of this pop up phenomenon and diminish this by change manufacturing processes of microaccelerometer sensor by electrostatic force.

• Journal of the Korean Society for Precision Engineering
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• v.27 no.2
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• pp.13-19
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• 2010

Due to the rapid spread of mobile handheld devices, industrial demands for micro-scale holes with a diameter of even smaller than $10{\mu}m$ in sapphire/silicon wafers have been increasing. Holes in sapphire wafers are for heat dissipation from LEDs; and those in silicon wafers for interlayer communication in three-dimensional integrated circuit (IC). We have developed a sapphire wafer driller equipped with a 532nm laser in which a cooling chuck is employed to minimize local heat accumulation in wafer. Through the optimization of process parameters (pulse energy, repetition rate, number of pulses), quality holes with a diameter of $30{\mu}m$ and a depth of $100{\mu}m$ can be drilled at a rate of 30holes/sec. We also have developed a silicon wafer driller equipped with a 355nm laser. It is able to drill quality through-holes of $15{\mu}m$ in diameter and $150{\mu}m$ in depth at a rate of 100holes/sec.