• 제어로봇시스템학회:학술대회논문집
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• 1989.10a
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• pp.421-426
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• 1989

Many of semiconductor manufacturing companies persuit automation of wafer fabrication to improve the yields and quality of their products. Development of real-time control system for wafer fabrication and wafer/cassette automatic transfer-system is the most important part to achieve the purpose. In this paper, SECS protocol proposed by SEMI is briefly reviewed and an implementation method of real-time monitoring and control system is suggested as one of the possible ways for wafer fabrication automation. The system consists of process equipments supporting SECS.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1264-1268
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• 2004

This paper presents a wafer motion modeling of the transfer unit and the control unit in the clean tube system, which was developed as a means for transferring the air-floated wafers inside the closed tube filled with the super clean airs. The motion in the transfer unit is modeled as a mass-spring-damper system where the recovering force by air jets issued from the perforated plate is modeled as a linear spring. The motion in the control unit is also modeled as another mass-spring-damper system, but in two dimensional systems. Experiments with a clean tube system built for 12-inch wafers show the validity of the presented force and motion models.

• Transactions of the Korean Society of Mechanical Engineers
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• v.16 no.4
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• pp.609-620
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• 1992

A numerical solution of temperature and thermally induced stress in a wafer during rapid thermal processing (R.T.P) is obtained, and an analysis of onset and propagation of slip is performed and compared with experiment. In order to calculate temperature distribution of a wafer in R.T.P system, heat conduction equation that incorporated with radiative and convective heat transfer model is solved, and the solution of the equation is calculated numerically using alternating direction implicit (A.D.I) method. In dealing with radiative heat transfer, a partially transparent body that absorbs the radiation energy is assumed and this transparent body undergoes multiple internal reflections and absorptions. Two dimensional (assuming plane stress) thermoelastic constitutive equation is used to calculate thermal stress induced in a wafer and finite element method is employed to solve the equation numerically. The stress resolved in the slip directions on the slip planes of silicon is compared with the yield stress of silicon in order to predict the slip. The result of the analysis shows that the wafer temperature at which slip occurs is affected by the heating rate of the R.T.P system. It is observed that once slip occurs in the wafer, the slip grows.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.427-431
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• 2005

In this study, 6' GaAs wafer bonding system is designed and optimized to bond 6 inches device wafer and material wafer. Bonding process is performed in vacuum environment and resin is used to bond two wafers. Vacuum module and double heating mechanisms are adopted to minimize wafer warpage and void. Structure and heat transfer analysis, et al of the core modules review the designed mechanisms are very effective in performance improvement. As a result, high productivity (tack time cut-down) and stabilized process can be obtained by reducing breakage failure of wafer.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.10a
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• pp.493-494
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• 2006

• Transactions of the Korean Society of Mechanical Engineers B
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• v.24 no.1
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• pp.9-20
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• 2000

An analysis of heat and mass transfer has been carried out for multi-wafer Low Pressure Chemical Vapor Deposition (LPCVD). Surface radiation analysis considering specular radiation among wafers, heaters, quartz tube and side plates of the reactor has been done to determine temperature distributions of 150 wafers in two dimensions. Velocity, temperature and concentration fields of chemical gases flowing in a reactor with multi-wafers have been then determined, which determines Si deposition growth rate and uniformity on wafers using two different surface reaction models. The calculation results of temperatures and Si deposition have been compared and found to be in a reasonable agreement with the previous experiments.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.11.1-11.1
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• 2011

We have developed a simple synthetic method for fabricating a wafer-scale colloidal crystal film of 2D crystals in a 1D stack based on a combination of two simple processes : the self-assembly of polystyrene (PS) nanospheres at the water-air interface and the layer-by-layer (LbL) scooping transfer technique. The main advantage of this approach is that it allows excellent control of the thickness (at a layer level) of the crystals and the formation of a vertical crack-free layer over a wafer-scale (4 inch). We investigate the optical and morphological properties of the PhC multilayers fabricated using various mono-sized colloidal crystals (250, 300, 350, 420, 580, 720, and 850 nm), and mixed binary colloidal crystals (300/350 and 250/350 nm).

• Journal of the Korean Society of Visualization
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• v.14 no.2
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• pp.25-30
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• 2016

The wafer temperature and its uniformity inside the LPCVD chamber were analyzed. The temperature uniformity at the end of the wafer load depends on the heat-insulating cap. The finite difference method was used to investigate the radiation and conduction heat transfer mechanisms, and the temperature field and heat diffusion in the LPCVD chamber was visualized. It was found that the temperature uniformity of the wafers could be controlled by the size and distance of the heat-insulating cap.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2011.06a
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• pp.495-496
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• 2011

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.743-746
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• 2003

We have successfully used hydrophobic direct-wafer bonding, along with H-induced layer splitting of Ge, to transfer 700nm think, single-crystal Ge films to Si substrates. Optical and electrical properties have been also observed on these samples. Triple-junction solar cell structures gown on these Ge/Si heterostructure templates show comparable photoluminescence intensity and minority carrier lifetime to a control structure grown on bulk Ge. When heavily doped p$^{+}$Ge/p$^{+}$Si wafer bonded heterostructures were bonded, ohmic interfacial properties with less than 0.3Ω$\textrm{cm}^2$ specific resistance were observed indicating low loss thermal emission and tunneling processes over and through the potential barrier. Current-voltage (I-V) characteristics in p$^{+}$Ge/pSi structures show rectifying properties for room temperature bonded structures. After annealing at 40$0^{\circ}C$, the potential barrier was reduced and the barrier height no longer blocks current flow under bias. From these observations, interfacial atomic bonding structures of hydrophobically wafer bonded Ge/Si heterostructures are suggested.ested.