• 한국정밀공학회지
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• 제21권10호
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• pp.26-33
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• 2004

Ultra precision grinding technology has been developed from the refinement of the abrasive, the development of high stiffness equipment and grinding skill. The conventional wafering process which consists of lapping, etching, 1 st, 2nd and 3rd polishing has been changed to the new process which consists of precision surface grinding, final polishing and post cleaning. Especially, the ultra precision grinding of wafer improves the flatness of wafer and the efficiency of production. Furthermore, it has been not only used in bare wafer grinding, but also applied to wafer back grinding and SOI wafer grinding. This paper focuses on the flatness of the ground wafer. Generally, the ground wafer has concave pronto because of the difference of wheel path density, grinding temperature and elastic deformation of the equipment. Wafer tilting is applied to avoid non-uniform material removal. Through the geometric analysis of wafer grinding process, the profile of the ground wafer is predicted by the development of profile simulator.

• 한국전기전자재료학회논문지
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• 제19권4호
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• pp.309-313
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• 2006

Pad surface characteristics such as roughness, groove and wear rate of pad have a effect on the within wafer non-uniformity(WIWNU) in chemical mechanical polishing(CMP). Although WIWNU increases as the uniformity of roughness(Rpk: Reduced peak height) becomes worse in an early stage of polishing time, WIWNU decreases as non-uniformity of the Rpk value. Also, WIWNU decreases with the reduction of the pad stiffness, though original mechanical properties of pad are unchanged by the grooving process. In addition, conditioning process causes the inequality of pad wear during in CMP. The profile of pad wear generated by the conditioning process has a significant effect on the WIWNU. These experiments results could help to understand the effect of pad surface characteristics in CMP.

• 한국전기전자재료학회논문지
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• 제12권1호
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• pp.27-34
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• 1999

We investigated the effect of mechanical back side damage in viewpoint of electrical and surface morphological characteristics in Czochralski silicon wafer. The intensity of mechanical damage was evaluated by minority carrier recombination lifetime by laser excitation/microwave reflection photoconductance decay technique, atomic force microscope, optical microscope, wet oxidation/preferential etching methods. The data indicate that the higher the mechanical damage degree, the lower the minority carrier lifetime, and surface roughness, damage depth and density of oxidation induced stacking fault increased proportionally.

• Journal of the Optical Society of Korea
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• 제14권2호
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• pp.163-169
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• 2010

Novel wafer-level fabrication of a glass ball-lens is realized for optoelectronic applications. A Pyrex wafer is bonded to a silicon wafer and cross-cut into a square-tile pattern, followed by wet-etching of the underlying silicon. Cubes of Pyrex on the undercut silicon are then turned into ball shapes by thermal reflow, and separated from the wafer by further etching of the silicon support. Radial variation and surface roughness are measured to be less than ${\pm}3\;{\mu}m$ and ${\pm}1\;nm$, respectively, for ball diameter of about $500\;{\mu}m$. A surface defect on the ball that is due to the silicon support is shown to be healed by using a silicon-optical-bench. Optical power-relay of the ball lens showed the maximum efficiency of 65% between two single-mode fibers on the silicon-optical-bench.

• 한국공작기계학회논문집
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• 제17권2호
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• pp.1-6
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• 2008

In recent years, developments in the semiconductor and electronic industries have brought a rapid increase in the use of large size silicon wafer. For further improvement of the ultra precision surface and flatness of Si wafer necessary to high density ULSI, it is known that polishing is very important. However, most of these investigation was experiment less than 300mm diameter. Polishing is one of the important methods in manufacturing of Si wafers and in thinning of completed device wafers. This study reports the machining variables that has major influence on the characteristic of wafer polishing. It was adapted to polishing pressure, machining speed, and the slurry mix ratio, the optimum condition is selected by ultra precision wafer polishing using load cell and infrared temperature sensor. The optimum machining condition is selected a result data that use a pressure and table speed data. By using optimum condition, it achieves a ultra precision mirror like surface.

• 반도체디스플레이기술학회지
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• 제8권2호
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• pp.31-35
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• 2009

In the silicon wafer polishing process, the mounting stage of silicon wafer on the ceramic carrier block has been using the polishing template which utilizes the porous surface instead of traditional wax mounting method. Here in this article, the experimental study is carried out in order to study the wafer demounting by water jet and the effects of operating conditions such as the water jet flowrate and the number of water jet nozzles on the wafer demounting time. It is found that the measured wafer demounting time is inversely proportional to the water flowrate per nozzle, regardless of number of nozzles used; implying that the stagnation pressure by the water jet impingement is the dominant key factor. Additionally, by using the transparent disk instead of wafer, the air bubble formation and growth is observed under the disk, making the passage of water flow, and subsequently demounting the wafer from the porous pad.

• 한국세라믹학회지
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• 제48권4호
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• pp.312-315
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• 2011

The effect of slurry composition and wafer flatness on a material removal rate (MRR) and resulting surface roughness which are evaluation parameters to determine the CMP characteristics of the on-axis 6H-SiC substrate were systematically investigated. 2-inch SiC wafers were fabricated from the ingot grown by a conventional physical vapor transport (PVT) method were used for this study. The SiC substrate after the CMP process using slurry added oxidizers into slurry consisted of KOH-based colloidal silica and nano-size diamond particle exhibited the significant MRR value and a fine surface without any surface damages. SiC wafers with high bow value after the CMP process exhibited large variation in surface roughness value compared to wafer with low bow value. The CMPprocessed SiC wafer having a low bow value of 1im was observed to result in the Root-mean-square height (RMS) value of 2.747 A and the mean height (Ra) value of 2.147 A.

• 디지털콘텐츠학회 논문지
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• 제5권4호
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• pp.251-256
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• 2004

반도체 집적회로를 만드는 토대가 되는 실리콘 웨이퍼의 표면은 고품질 회로를 구성하기 위해 극도의 평탄도가 요구되므로 평탄도는 양질의 웨이퍼를 보증하는 가장 중요한 요소이다. 따라서 실리콘웨이퍼 생산의 10개의 공정 중 거칠어진 웨이퍼 표면을 고도의 평탄도를 갖도록 연마하는 폴리싱공정은 매우 중요시 되는 생산라인이다. 현재 이 공정에서는 담당 엔지니어가 웨이퍼의 모형을 측정장비의 모니터에서 육안으로 관찰하여 판단하고 평탄도를 높이기 위한 제어를 하고 있다. 그러나 사람에 의한 것이므로 많은 경험이 필요하고 일일이 체크해야하는 번거로움이 있다. 본 연구는 이러한 비효율적인 작업의 효율화를 위해 웨이퍼의 모형을 디지털 컨텐츠화하여 폴리싱 공정에 있어 평탄도를 사람이 아닌 시스템에 의해 자동으로 측정하여 제어하는 알고리즘을 제안한다. 또한 제안한 전체 웨이퍼 평탄도 추정알고리즘을 토대로 실제 현장에서 쓰이는 웨이퍼 각 사이트별 평탄도를 측정하기 위한 사이트두께 추정 알고리즘을 제안한다.

• 마이크로전자및패키징학회지
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• 제15권2호
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• pp.63-67
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• 2008

전자산업의 소형화와 경량화 추세에 맞추어 최근 집적 칩(IC)이나 패키지를 적층시키는 삼차원 집적화(3D integration) 기술 개발은 차세대 핵심기술로 중요시되고 있다. 본 연구에서는 삼차원 집적화 공정 기술 중 하나인 초박막 실리콘 웨이퍼 연삭(grinding)공정이 웨이퍼 표면에 미치는 영향에 대해서 조사하였다. 실리콘 웨이퍼를 약 $30{\mu}m$과 $50{\mu}m$ 두께까지 연삭한 후, 미세연삭(fine grinding) 단계까지 처리된 시편을 건식 연마(dry polishing) 또는 습식 애칭(wet etching)으로 표면 처리된 시편들과 비교 분석하였다. 박막 웨이퍼 두께는 전계방시형 주사전자현미경과 적외선 분광기로 측정하였고, 표면 특성 분석을 위해선 표면주도(roughness), 표면손상(damage), 경도를 원자현미경, 투과정자현미경 그리고 나노인덴터(nano-indentor)를 이용하여 측정하였다. 표면 처리된 시편의 특성이 표면 처리되지 않은 시편보다 표면주도와 표면손상 등에서 현저히 우수함을 확인 할 수 있었으나, 경도의 경우 표면 처리의 유무에 관계없이 기존의 벌크(bulk)실리콘 웨이퍼와 오차범위 내에서 동일한 것으로 보였다.

• 한국응용과학기술학회지
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• 제16권1호
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• pp.33-40
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• 1999

We used Cu as a representative of metals to be directly adsorbed on the bare Si surface and studied its removal DHF, DHF-$H_2O_2$ and BHF solution. It has been found that Cu ion in DHF adheres on every Si wafer surface that we used in our study (n, p, n+, p+) especially on the n+-Si surface. The DHF-$H_2O_2$ solution is found to be effective in removing metals featuring high electronegativity such as Cu from the p-Si and n-Si wafers. Even when the DHF-$H_2O_2$ solution has Cu ions at the concentration of 1ppm, the solution is found effective in cleaning the wafer. In the case the n+-Si and p+-Si wafers, however, their surfaces get contaminated with Cu When Cu ion of 10ppb remains in the DHF-$H_2O_2$ solution. When BHF is used, Cu in BHF is more likely to contaminate the n+-Si wafer. It is also revealed that the surfactant added to BHF improve wettability onto p-Si, n-Si and p+-Si wafer surface. This effect of the surfactant, however, is not observed on the n+-Si wafer and is increased when it is immersed in the DHF-$H_2O_2$ solution for 10min. The rate of the metallic contamination on the n+-Si wafer is found to be much higher than on the other Si wafers. In order to suppress the metallic contamination on every type of Si surface below 1010atoms/cm2, the metallic concentration in ultra pure water and high-purity DHF which is employed at the final stage of the cleaning process must be lowered below the part per trillion level. The DHF-$H_2O_2$ solution, however, degrades surface roughness on the substrate with the n+ and p+ surfaces. In order to remove metallic impurities on these surfaces, there is no choice at present but to use the $NH_4OH-H_2O_2-H_2O$ and $HCl-H_2O_2-H_2O$ cleaning.