• 한국전기전자재료학회논문지
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• 제19권10호
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• pp.894-900
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• 2006

This paper reports the fabrication and characterization of $32{\times}32$ thermal cantilever array for nano-scaled memory device applications. The $32{\times}32$ thermal cantilever array with integrated tip heater has been fabricated with micro-electro-mechanical systems(MEMS) technology on silicon on insulator(SOI) wafer using 9 photo masking steps. All of single-level cantilevers(1,024 bits) have a p-n junction diode in order to eliminate any electrical cross-talk between adjacent cantilevers. Nonlinear electrical characteristic of fabricated thermal cantilever shows its own thermal heating mechanism. In addition, n-channel high-voltage MOSFET device is integrated on a wafer for embedding driver circuitry.

• 한국전기전자재료학회논문지
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• 제11권2호
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• pp.95-100
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• 1998

A helical inductively coupled plasma asher, which produces low energy and high density plasma, has been built and investigated for photoresist stripping process. Oxygen ion density in the order of $10^{11}/cm^3$ is measured by Langmuir probe, and higher oxygen radical density is observed by Optical Emission Spectrometer. As RF source power is increased, the plasma density and thus photoresist stripping rate are increased. Independent RF bias power to the wafer stage provides a dc bias to the wafer and an ability to add the ion assisted reaction. At 1 KW of the source power, the coupling mechanism of the RF power to the plasma is changed from the inductive mode to the capacitive one at about 1 Torr. This change causes the plasma density and ashing rate decreases abruptly. The critical pressure of the mode change becomes larger with larger RF power.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권3호
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• pp.133-139
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• 2007

Future MEMS systems will be composed of larger varieties of devices with very different functionality such as electronics, mechanics, optics and bio-chemistry. Integration technology of heterogeneous devices must be developed. This article first deals with the current development trend of new fabrication technologies; those include self-assembling of parts over a large area, wafer-scale encapsulation by wafer-bonding, nano imprinting, and roll-to-roll printing. In the latter half of the article, the concept towards the heterogeneous integration of devices and functionality into micro/nano systems is described. The key idea is to combine the conventional top-down technologies and the novel bottom-up technologies for building nano systems. A simple example is the carbon nano tube interconnection that is grown in the via-hole of a VLSI chip. In the laboratory level, the position-specific self-assembly of nano parts on a DNA template was demonstrated through hybridization of probe DNA segments attached to the parts. Also, bio molecular motors were incorporated in a micro fluidic system and utilized as a nano actuator for transporting objects in the channel.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.75-78
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• 2000

This paper is estimated to enhance yield improvement and device reliability using PDM(plasma damage monitoring) system capable of in-suit detection about plasma nonuniformity. PDM Tool is the non-contact method of wafer and surface potential electrode(kelvin probe). Its tool measures Vox(oxide barrier) with charge created by plasma. It's possible to inspect the wafer damage generated by plasma charge and analysis of in-situ monitoring data. we obtained the good data which is continuously prevented from plasma damage using its tool for 10weeks. This tool is contributed to preventive steps contemporaneously inspecting the difference of inter-chamber.

• Tribology and Lubricants
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• 제17권4호
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• pp.276-282
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• 2001

Nano adhesion between SPM (scanning probe microscope) tips and 075 (octadecyltrichlorosilane) SAM (self-assembled monolayer) was experimentally studied. Tests were performed to measure the nano adhesion and friction in both AFM(atomic force microscope) and LFM(lateral force microscope) modes in various conditions of relative humidity. OTS SAM was formed on Si-wafer (100) surfaces, and Si$_3$N$_4$ tips of different radius of curvature were used. When the surface was hydrophobic, the adhesion and friction forces were found lower than those of bare Si-wafer. Results also showed that micro-adhesion force increased as the relative humidity and the tip radius of curvature increased. The main parameter for affecting the micro-adhesion was found absorbed humidity on the contact surface. These results were discussed with the JKR model and a capillary force caused by absorbed water.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2000년도 제18회 학술발표회 논문개요집
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• pp.180-180
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• 2000

Plasma source ion implantation is a new doping technique for the formation of shallow junction with the merits of high dose rate, low-cost and minimal wafer charging damage. In plasma source ion implantation process, the wafer is placed directly in the plasma of the appropriate dopant ions. Negative pulse bias is applied to the wafer, causing the dopant ions to be accelerated toward the wafer and implanted below the surface. In this work, inductively couples plasma was generated by anodized Al antenna that was located inside the vacuum chamber. The outside wall of Al chamber was surrounded by Nd-Fe-B permanent magnets to confine the plasma and to enhance the uniformity. Before implantation, the wafer was pre-sputtered using DC bias of 300B in Ar plasma in order to eliminate the native oxide. After cleaning, B2H6 (5%)/H2 plasma and negative pulse bias of -1kV to 5 kV were used to form shallow p+/n junction at the boron dose of 1$\times$1015 to 5$\times$1016 #/cm2. The as-implanted samples were annealed at 90$0^{\circ}C$, 95$0^{\circ}C$ and 100$0^{\circ}C$during various annealing time with rapid thermal process. After annealing, the sheet resistance and the junction depth were measured with four point probe and secondary ion mass spectroscopy, respectively. The doping uniformity was also investigated. In addition, the electrical characteristics were measured for Schottky diode with a current-voltage meter.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 하계학술대회 논문집 C
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• pp.1634-1636
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• 2004

반도체 웨이퍼의 면저항을 정밀 측정하는 대표적인 두가지 방법인 4탐침(four point probe)방법과 van der Pauw방법으로 반도체 웨이퍼의 면저항을 비교평가 하였다. 4탐침방법에 의한 측정 시스템을 사용하여 웨이퍼의 전체 면에 대하여 면저항을 측정하고, 같은 웨이퍼의 가장자리 네 지점에 탐침 전극을 구성한 후 van der Pauw 방법으로 면저항을 측정한 결과 4탐침 방법에 의한 측정결과를 기준으로 1 %이하의 일치도를 나타냈다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권3호
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• pp.259-262
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• 2013

Multi-site testing is considered as a solution to reduce test costs. This paper presents a new channel sharing architecture that enables I/O pins to share automatic test equipment (ATE) channels using simple circuitry such as tri-state buffers, AND gates, and multiple-input signature registers (MISR). The main advantage of the proposed architecture is that it is implemented on probe cards and does not require any additional circuitry on a target device under test (DUT). In addition, the proposed architecture can perform DC parametric testing of the DUT such as leakage testing, even if the different DUTs share the same ATE channels. The simulation results show that the proposed architecture is very efficient and is applicable to both wafer testing and package testing.

• 마이크로전자및패키징학회지
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• 제24권3호
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• pp.77-81
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• 2017

Pulse electroplating of Ni-P alloy was studied to fulfill the material requirement to the advanced vertical probe tip in wafer probe card. The major concerns are for the electrical conductivity and yield strength. Plating parameters such as current density, duty cycle and solution components were examined to obtain the nanocrystal structure and proper percentage of phosphorus, leading to how to control the nanocrystal grain growth and precipitation of $Ni_3P$ after heat treatment. Among the parameters, the amount of phosphorus acid was the main factor affecting on the grain size and sheet resistance, and the amount of 0.1 gram was appropriate. Since hardness in Ni-P alloy is increased by as-plated nanocrystal structure plus precipitation of $Ni_3P$, the concentration of P less than 15 at% was better choice for the grain coarsening without minus in hardness value. The following heat treatment made grain growth and dispersion of precipitates adjustable to meet the target limit of resistance of $100m{\Omega}$ and hardness number of over 1000Hv. The Ni-P alloy will be a candidate for the substitute of the conventional probe tip material.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권4호
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• pp.293-298
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• 2006

Thermopiezoelectric method, using poly silicon heater and a piezoelectric sensor, was proposed for writing and reading in a probe based data storage system. Resistively heated tip writes data bits while scanning over a polymer media and piezoelectric sensor reads data bits from the self-generated charges induced by the deflection of the cantilever. 34${\times}$34 array of thermopiezoelectric nitride cantilevers were fabricated by a single step wafer level transfer method. We analyzed the noise level of the charge amplifier and measured the noise signal. With the sensor and the charge amplifier 20mn of deflection could be detected at a frequency of 10KHz. Reading signal was obtained from the cantilever array and the sensitivity was calculated.