• Tribology and Lubricants
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• v.21 no.1
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• pp.1-7
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• 2005

Effect of Surface roughness on nanoscale adhesion was studied experimentally by using colloidal probe technique. Glass micro balls having the radius of $3.3\~17.4{\mu}m$ were glued at the end of AFM cantilevers to prepare colloidal probes. Adhesion force between the colloidal probe and Si-wafer was measured using pull-off force measuring method. Results showed that the measured adhesion forces are not the function of the radius of the glued balls because the ball surfaces are rough. It is also found that roughness parameters such as $R_a,\;R_q\;and\;R_{max}$ do not have important role on nanoscale adhesion. In order to find the effect of surface roughness on nanoscale adhesion, the bearing areas were extracted from the measured topography of glued balls. After normalizing the measured adhesion force with the bearing area, it was found that the normalized adhesion force kept constant as function of the radius of glued ball.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.267-269
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• 2003

반도체 웨이퍼 및 각종 박막의 면/비저항(sheet/resistivity resistance)의 측정에 비교적 간단히 측정할 수 있고 측정정확도가 높은 4탐침(four-point probe)방법이 널리 사용되고 있다 또한 4탐침 측정방법은 높은 분해능의 contour map작성과 ion implantation의 doping accuracy 및 doping uniformity의 측정에도 사용된다. 최근 재료의 소형, 박막화 경향으로 볼 때 정확한 비저항 측정의 필요성이 요구되고 있으며 이에 따라 4탐침 측정기술인 single 및 dual configuration method로 실리콘 웨이퍼에 대한 비저항의 측정 정확도를 고찰한 결과 dual configuration 측정방법이 single configuration측정 방법에 비하여 정밀 정확도가 더 좋은 것으로 고찰되었다.

• Journal of Sensor Science and Technology
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• v.21 no.1
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• pp.34-38
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• 2012

We have developed a cost effective test socket for ball grid array(BGA) integrated circuit(IC) packages using BeCu metal sheet as a test probe. The BeCu furnishes the best combination of electrical conductivity and corrosion resistance. The probe of the test socket was designed with a BeCu cantilever. The cantilever was designed with a length of 450 ${\mu}m$, a width of 200 ${\mu}m$, a thickness of 10 ${\mu}m$, and a pitch of 650 ${\mu}m$ for $11{\times}11$ BGA. The fabrication of the test socket used techniques such as through-silicon-via filling, bonding silicon wafer and BeCu metal sheet with dry film resist(DFR). The test socket is applicable for BGA IC chip.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.11
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• pp.990-995
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• 2005

This paper reports the fabrication and characterization of $5\;\times\;5$ thermal cantilever array for nano-scaled memory device application. The $5\;\times\;5$ thermal cantilever array with integrated tip heater has been fabricated with MEMS technology on SOI wafer using 7 photo masking steps. All single-level cantilevers have a diode in order to eliminate any electrical cross-talk between adjacent tips. Electrical measurements of fabricated thermal cantilever away show its own thermal heating mechanism. Thermal heating is demonstrated by the reflow of coated photoresist on the cantilever array surface.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.2
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• pp.11-15
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• 2013

The wafer bonding process becomes a flexible approach to material and device integration. The bonding strength in 3-dimensional process is crucial factor in various interface bonding process such as silicon to silicon, silicon to metals such as oxides to adhesive intermediates. A measurement method of bonding strength was proposed by utilizing AFM applied CNT probe tip which indicated the relative simplicity in preparation of sample and to have merit capable to measure regardless type of films. Also, New Tool was utilized to measure of tip radius. The cleaned $SiO_2$-Si bonding strength of SPFM indicated 0.089 $J/m^2$, and the cleaning result by RCA 1($NH_4OH:H_2O:H_2O_2$) measured 0.044 $J/m^2$, indicated negligible tolerance which verified the possibility capable to measure accurate bonding strength. And it could be confirmed the effective bonding is possible through SPFM cleaning.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.438-439
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• 2013

Microelectronic devices의 접촉저항의 향상을 위해 Metal silicides의 형성 mechanism과 전기적 특성에 대한 연구가 많이 이루어지고 있다. 지난 수십년에 걸쳐, Ti silicide, Co silicide, Ni silicide 등에 대한 개발이 이루어져 왔으나, 계속적인 저저항 접촉 소재에 대한 요구에 의해 최근에는 Rare earth silicide에 관한 연구가 시작되고 있다. Rare-earth silicide는 저온에서 silicides를 형성하고, n-type Si과 낮은 schottky barrier contact (~0.3 eV)를 이룬다. 또한, 비교적 낮은 resistivity와 hexagonal AlB2 crystal structure에 의해 Si과 좋은 lattice match를 가져 Si wafer에서 high quality silicide thin film을 성장시킬 수 있다. Rare earth silicides 중에서 ytterbium silicide는 가장 낮은 electric work function을 갖고 있어 낮은 schottky barrier 응용에서 쓰이고 있다. 이로 인해, n-channel schottky barrier MOSFETs의 source/drain으로써 주목받고 있다. 특히 ytterbium과 molybdenum co-deposition을 하여 증착할 경우 thin film 형성에 있어 안정적인 morphology를 나타낸다. 또한, ytterbium silicide와 마찬가지로 낮은 면저항과 electric work function을 갖는다. 그러나 ytterbium silicide에 molybdenum을 화합물로써 높은 농도로 포함할 경우 높은 schottky barrier를 형성하고 epitaxial growth를 방해하여 silicide film의 quality 저하를 야기할 수 있다. 본 연구에서는 ytterbium과 molybdenum의 co-deposition에 따른 silicide 형성과 전기적 특성 변화에 대한 자세한 분석을 TEM, 4-probe point 등의 다양한 분석 도구를 이용하여 진행하였다. Ytterbium과 molybdenum을 co-deposition하기 위하여 기판으로 $1{\sim}0{\Omega}{\cdot}cm$의 비저항을 갖는 low doped n-type Si (100) bulk wafer를 사용하였다. Native oxide layer를 제거하기 위해 1%의 hydrofluoric (HF) acid solution에 wafer를 세정하였다. 그리고 고진공에서 RF sputtering 법을 이용하여 Ytterbium과 molybdenum을 동시에 증착하였다. RE metal의 경우 oxygen과 높은 반응성을 가지므로 oxidation을 막기 위해 그 위에 capping layer로 100 nm 두께의 TiN을 증착하였다. 증착 후, 진공 분위기에서 rapid thermal anneal(RTA)을 이용하여 $300{\sim}700^{\circ}C$에서 각각 1분간 열처리하여 ytterbium silicides를 형성하였다. 전기적 특성 평가를 위한 sheet resistance 측정은 4-point probe를 사용하였고, Mo doped ytterbium silicide와 Si interface의 atomic scale의 미세 구조를 통한 Mo doped ytterbium silicide의 형성 mechanism 분석을 위하여 trasmission electron microscopy (JEM-2100F)를 이용하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.3
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• pp.661-669
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• 1999

A probe card is one of the most important pan of test systems as testing IC(integrated circuit) chips. This work was related to bump-type silicon vertical probe card which enabled simultaneous tests for multiple semiconductor chips. The probe consists of silicon cantilever with bump tip. In order to obtain optimum size of the cantilever, the dimensions were determined by FEM(finite element method) analysis. The probe was fabricated by RIE(reactive ion etching), isotropic etching, and bulk-micromachining using SDB(silicon direct bonding) wafer. The optimum height of the bump of the probe detemimed by FEM simulation was 30um. The optimum thickness, width, and length of the cantilever were 20 $\mum$, 100 $\mum$,and 400 $\mum$,respectively. Contact resistance of the fabricated probe card measured at contact resistance testing was less than $2\Omega$. It was also confirmed that its life time was more than 20,000 contacts because there was no change of contact resistance after 20,000 contacts.

• Korean Journal of Materials Research
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• v.29 no.9
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• pp.547-552
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• 2019

In the present study, the thermal conductivity of a silicon nitride($Si_3N_4$) thin-film is evaluated using the dual-wavelength pump-probe technique. A 100-nm thick $Si_3N_4$ film is deposited on a silicon (100) wafer using the radio frequency plasma enhanced chemical vapor deposition technique and film structural characteristics are observed using the X-ray reflectivity technique. The film's thermal conductivity is measured using a pump-probe setup powered by a femtosecond laser system of which pump-beam wavelength is frequency-doubled using a beta barium borate crystal. A multilayer transient heat conduction equation is numerically solved to quantify the film property. A finite difference method based on the Crank-Nicolson scheme is employed for the computation so that the experimental data can be curve-fitted. Results show that the thermal conductivity value of the film is lower than that of its bulk status by an order of magnitude. This investigation offers an effective way to evaluate thermophysical properties of nanoscale ceramic and dielectric materials with high temporal and spatial resolutions.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.7
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• pp.831-841
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• 2010

The conventional vertical probe has the thin and long signal path that makes transfer characteristic of probe worse because of the S-shaped structure. So we propose the new vertical probe structure that has branch springs in the S-shaped probe. It makes closed loop when the probe mechanically connects to the electrode on a wafer. We fabricated the proposed vertical probe and measured the transfer characteristic and mechanical properties. Compared to the conventional S-shaped vertical probe, the proposed probe has the overdrive that is 1.2 times larger and the contact force that is 2.5 times larger. And we got the improved transfer characteristic by 1.4 dB in $0{\sim}10$ GHz. Also we developed the simulation model of the probe card by using full-wave simulator and the simulation result is correlated with measurement one. As a result of this simulation model, the cantilever probe and PCB have the worst transfer characteristic in the probe card.

• Korean Journal of Materials Research
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• v.23 no.6
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• pp.322-328
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• 2013

The relationship the between electrical properties and surface roughness (Ra) of a wet-etched silicon wafer were studied. Ra was measured by an alpha-step process and atomic force microscopy (AFM) while varying the measuring range $10{\times}10$, $40{\times}40$, and $1000{\times}1000{\mu}m$. The resistivity was measured by assessing the surface resistance using a four-point probe method. The relationship between the resistivity and Ra was explained in terms of the surface roughness. The minimum error value between the experimental and theoretical resistivities was 4.23% when the Ra was in a range of $10{\times}10{\mu}m$ according to AFM measurement. The maximum error value was 14.09% when the Ra was in a range of $40{\times}40{\mu}m$ according to AFM measurement. Thus, the resistivity could be estimated when the Ra was in a narrow range.