• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.6
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• pp.432-440
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• 2010

In this paper, a LC series resonant boost converter using a single switch is proposed. The proposed topology contains additional passive elements in the conventional boost converter and performs Zero Voltage Switching(ZVS) without an additional auxiliary switch when a main switch turned on and off. The switch off time of the proposed system determined by LC series resonance, thus a on-time variable Pulse Frequency Modulation(PFM) method is adapted to control output voltage in the proposed converter. Operational modes of the proposed topology are divided with respected to the current conduction paths and then through the theoretical analysis and experimental results, operational modes and characteristics of the proposed converter are verified.

• Journal of Power Electronics
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• v.19 no.1
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• pp.190-200
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• 2019

The flyback converter, which can be regarded as a nonlinear time-varying system, has complex dynamics and nonlinear behaviors. These phenomena can affect the stability of the converter. To simplify the modeling process and retain the information of the output capacitor branch, a special sampled-data model of a peak current-mode (PCM) controlled flyback converter is established in this paper. Based on this, its dynamic behaviors are analyzed, which provides guidance for designing the circuit parameters of the converter. With the critical stability boundary equation derived by a Jacobian matrix, the stable operation range with a varied output capacitor, proportional coefficient of error the amplifier, input voltage, reference voltage and slope of the compensation ramp of a PCM controlled flyback converter are investigated in detail. Research results show that the duty ratio should be less than 0.5 for a PCM controlled flyback converter without ramp compensation to operate in a stable state. The stability regions in the parameter space between the output capacitor and the proportional coefficient of the error amplifier are enlarged by increasing the input voltage or by decreasing the reference voltage. Furthermore, the ramp compensation also can extend to the stable region. Finally, time-domain simulations and experimental results are presented to verify the theoretical analysis results.

• Journal of Power Electronics
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• v.15 no.1
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• pp.39-53
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• 2015

This paper presents the regulation of the output voltage and inductor currents in a Single Ended Primary Inductor Converter (SEPIC), operating in the continuous conduction mode (CCM) using a sliding mode controller. Owing to the time varying nature of the SEPIC converter, designing a feedback controller is a challenging task. In order to improve the dynamic performance of the SEPIC, a Sliding Mode Controller (SMC) is developed. The developed SMC is designed by using a state space average model. The performance of the developed controller with the SEPIC converter is validated at different working conditions through Matlab simulations. It is also compared with the performance while using a PI controller. The results show that the designed controller gives very good output voltage regulation under different operating conditions such as a varying input voltage, changes in the load and component variations. A 48V, 46W experimental setup for has been developed in an analog platform to validate the performance of the proposed SMC.

• The Transactions of the Korean Institute of Power Electronics
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• v.1 no.1
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• pp.38-46
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• 1996

The commutation operation of the current source converter for switched reluctance motor drives is analyzed in this paper. The commutation operation in the current source converter consists of two modes. At turn-off of phase switch, the phase current decreases sinusoidally, and the sum of two phase currents during commutation period is constant. At this time, the capacitor voltage increases quickly with changing polarity and decreases slowly when another phase switches turn on or off. Frequency of step-down DC chopper in the current source converter is low because of the dump such as BJTs and GTOs are possible as phase switches instead of Power MOSFET and IGBTS. They may result in reductions of conduction losses and manufacturing cost in the current source converter comparing to the voltage source converter of SRM.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.1
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• pp.37-42
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• 2021

This paper presents a jitter and phase noise characteristic improved phase-locked loop (PLL) with loop filter voltage detector(LFVD) and frequency voltage converter(FVC). Loop filter output voltage variation is determined through a circuit made of resistor and capacitor. The output signal of a small RC time constant circuit is almost the same as to loop filter output voltage. The output signal of a large RC time constant circuit is the average value of loop filter output voltage and becomes a reference voltage to the added LFVD. The LFVD output controls the current magnitude of sub-charge pump. When the loop filter output voltage increases, LFVD decreases the loop filter output voltage. When the loop filter output voltage decreases, LFVD increases the loop filter output voltage. In addition, FVC also improves the phase noise characteristic by reducing the loop filter output voltage variation. The proposed PLL with LFVD and FVC is designed in a 0.18um CMOS process with 1.8V power voltage. Simulation results show 0.854ps jitter and 30㎲ locking time.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.286-290
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• 2001

This paper describes an improved short-circuit protection method with a boost type rectifier using a multilevel ac/dc power converter. The output dc power of the proposed converter can be disconnected from the load within several hundred microseconds at the instant of short-circuit fault. Once the fault has been cleared the dc power is reapplied to the load. The rising time of the dc load voltage is as small as several hundred microseconds, and there is no overshoot of the dc voltage because the dc output capacitors hold undischarged state. The converter, which employs the proposed method, has the characteristics of a simplified structure, reduced cost, weight, and volume compared with a conventional power supply, which has frequent output short-circuits. Experimental results are presented to verify the usefulness of the proposed converter.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.483-485
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• 2010

A 200kS/s 10-bit successive approximation(SA) ADC with a rail-to-rail input range is proposed. The proposed SA ADC consists of DAC, comparator, and successive approximation register(SAR) logic. The folded-type capacitor DAC with the boosted NMOS switches is used to reduce the power consumption and chip area. Also, the time-domain comparator which uses a fully differential voltage-to-time converter improves the PSRR and CMRR. The SAR logic uses the flip-flop with a half valid window, it results in the reduction of the power consumption and chip area. The proposed SA ADC is designed by using a $0.18{\mu}m$ CMOS process with 1V supply.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.62 no.3
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• pp.145-150
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• 2013

A novel AC to DC PWM converters with unity input power factor are proposed to overcome the above shortcoming. The main function of these converters is to shape the input line current to force it exactly in phase with the input AC voltage. Therefore, the input power factor can be improved to near unity and the input current harmonics can be eliminated. In this paper, half-bridge converter with two active switches and two diodes are utilized for low-cost type UPS configuration. By having only two semiconductors in the current path at any time, losses can be reduced over the conventional boost topology. Also, this converter provides controllable dc-link voltage, high power factor, and low cost type converter by simple power circuits. Simulation results show that the proposed half-bridge converter/inverter control technique can be applied to single-phase low-cost type UPS systems successfully.

• Proceedings of the KIEE Conference
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• 2006.04b
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• pp.267-269
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• 2006

In this paper, a new single phase voltage sag/swell compensator using direct power conversion is introduced. A new compensator consists of input/output filter, series transformer and direct ac-ac converter, which is a single-phase back-to-back PWM converter without dc-link capacitors. Advantages of the proposed compensator include: simple power circuit by eliminating dc-link electrolytic capacitors and thereby, improved reliability and increased life time of the entire compensator; simple PWM strategy to compensate voltage sag/swell at the same time and reduced switching losses in the ac-ac converter. Further, the proposed scheme is able to adopt simple switch commutation method without requiring complex four-step commutation method commonly required in the direct power conversion. Simulation results are shown to demonstrate the advantages of the new compensator and PWM strategy.

• Proceedings of the KIEE Conference
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• 2006.07b
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• pp.1014-1015
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• 2006

In this paper, a new single phase voltage sag/swell compensator using direct power conversion is introduced. A new compensator consists of input/output filter, series transformer and direct at-ac converter, which is a single-phase back-to-back PWM converter without dc-link capacitors. Advantages of the proposed compensator include: simple power circuit by eliminating dc-link electrolytic capacitors and thereby, improved reliability and increased life time of the entire compensator; simple PWM strategy to compensate voltage sag/swell at the same time and reduced switching losses in the ac-ac converter. Further, the proposed scheme is able to adopt simple switch commutation method without requiring complex four-step commutation method commonly required in the direct power conversion. Simulation results are shown to demonstrate the advantages of the new compensator and PWM strategy.