• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.72-78
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• 2009

This paper proposes a low phase noise ring voltage controlled oscillator(VCO) with a standard $0.13{\mu}m$ CMOS process for PLL circuit using the VCO-gain-controlled Delay cell. The proposed Delay cell architecture with a active resistor using a MOS transistor. This method can reduced a VCO gain so that improve phase noise. And, Delay cell consist of Wide-Swing Cascode current mirror, Positive Latch and Symmetric load for low phase noise. The measurement results demonstrate that the phase noise is -119dBc/Hz at 1MHz offset from 1.9GHz. The VCO gain and power dissipation are 440MHz/V and 9mW, respectively.

• Journal of the Microelectronics and Packaging Society
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• v.3 no.2
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• pp.51-56
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• 1996

각종 통신기기의 주파수 합성기 등에 광범위하게 응용되고 있는 전압제어 발진기에 서 캐리어 대 잡음비(C/N비:Carrier noise Ratio)특성이 매우 중요하다. 특히 휴대용 단말기 에 쓰이는 소형 저소비전려의 VCO는 위상 잡음의 억제가 필수적이다. VCO의 C/N비 특성 은 공진회로의 선택도 Q와 능동소자의 각종 파라미터들 그리고 발전전력과 밀접한 관계가 있다. 본 논문에서는 CAD를 이용하여 우수한 C/N비를 갖는 900MHz대 VCO의 최적화 설 계방버을 제시하고 그 결과를 기초로 우수한 저잡은 VCO를 실현하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.12
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• pp.2439-2447
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• 1994

In this paper, We analyze Colpitts type voltage contrqlled oscillator(VCO) used in personal handheld phone using a nonlinear analysis with third-order model. The resul shows the non-exponentially decaying shifting bias superimposed on the oscillator output which is different with the exponentially decaying shifting bias from the linear analysis. The stable oscillation criterion during a frequency change in a design of VOC can be also determined using proposed non-linear analysis. The theory is confirmed using PSPICE simulation and the experimental result of GaAs VCO matched very well with the theory.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.1
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• pp.74-79
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• 2002

The EM(Engineering Model) VCO(Voltage Controlled Oscillator) is nonlinear designed for LO(Local Oscillator) of Ka-band satellite transponder. The microstripline coupled with dielectric resonator is implemented as a high impedance inverter to improve the phase noise, and the quality factor of resonant circuit can be transferred to active device with the enhanced loaded quality factor. The developed VCO has the oscillating tuning range of 9.7965~9.8032 GHz for the control voltage range of 0~12 V. This VCO requires the DC power of 8 V and 17 mA. The phase noise characteristics are -96.51 dBc/Hz @10 KHz and -116.5 dBc/Hz @100 KHz, respectively. And, the output power of 7.33 dBm is measured.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.8 no.4
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• pp.46-52
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• 2009

In this paper, a novel VCO (Voltage Controlled Oscillator) structure is proposed to achieve the characteristic of low phase noise and a wide frequency tuning range. The proposed scheme adopts an impedance transforming technique to change a series resonance into a parallel resonance for maximizing the susceptance slope parameter. The manufactured VCO shows a frequency tuning bandwidth of 600MHz from 10.1GHz to 10.7GHz with a tuning voltage varying from 0 to 9V, an excellent phase noise below -119dBc/Hz@1MHz offset. The harmonic suppression is measured above 28dB.

• The Journal of Korean Institute of Information Technology
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• v.16 no.11
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• pp.61-68
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• 2018

This paper describes design of a 10.525 GHz self oscillating mixer semiconductor IC chip combining voltage controlled oscillator and frequency mixer using silicon CMOS technology for Doppler radar applications. The p-core type VCO included in the self oscillating mixer minimizes the noise contained in the transmitted signal. This noise minimization increases the sensing distance and acts in a direction favorable to the reaching distance and the sensitivity of the motion detection sensor. Simulation results for phase noise show that a VCO designed as a P-core has a noise characteristic of -106.008 dBc / Hz at 1 MHz offset and -140.735 dBc / Hz at 25 MHz offset compared to a VCO designed with N-core and NP-core showed excellent noise characteristics. If a self-oscillating mixer is implemented using a p-core designed VCO in this study, a motion sensor with excellent range and reach sensitivity will be produced.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.35-43
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• 2011

In this paper, an analysis on I/Q mismatch characteristics of a quadrature LC VCO(Voltage controlled oscillator) is presented. Based on this analysis, a new I/Q mismatch compensator is proposed. The proposed I/Q mismatch compensator utilizes an amplitude mismatch detector rather than the conventional phase mismatch detector requiring much more wide frequency bandwidth. To verify the proposed circuit, a 2.5GHz quadrature LC VCO was designed in a $0.18{\mu}m$ CMOS process and tested. Test results show that an amplitude mismatch detector achieves similar I/Q mismatch compensation performance as that of the conventional phase mismatch detector. The I/Q mismatch compensator consumes 0.4mA from 1.8V supply voltage and occupies $0.04mm^2$.

• Journal of IKEEE
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• v.12 no.3
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• pp.172-175
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• 2008

An improved triangular/square-wave VCO using OTAs is presented. It consists of two OTAs, a timing capacitor, and a resistor. A prototype circuit built with commercially available components exhibits less than 0.01% nonlinearity in its current-to-frequency transfer characteristic from 0.2 to 14 kHz and 450 ppm/$^{\circ}C$ temperature coefficient of frequency over $-20^{\circ}C$ to $40^{\circ}$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.255-265
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• 2012

This paper presents a 15-GHz multiphase rotary traveling-wave voltage-controlled oscillator (RTW VCO) where a shielded coplanar stripline (CPS) is exploited to provide better shielding protection and lower phase noise at a moderate cost of characteristic impedance and power consumption. Test chips were implemented in a standard 90-nm CMOS process, demonstrating the measured results of 2-GHz frequency tuning range, -11.3-dBm output power, -109.6-dBc/Hz phase noise at 1-MHz offset, and 2-ps RMS clock jitter at 15 GHz. The chip core occupies the area of $0.2mm^2$ and dissipates 12 mW from a single 1.2-V supply.

• Journal of IKEEE
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• v.14 no.1
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• pp.40-46
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• 2010

This paper describes a clock and data recovery (CDR) circuit that supports dual data rates of 2.7Gbps and 1.62Gbps for DisplayPort standard. The proposed CDR has a dual mode voltage-controlled oscillator (VCO) that changes the operating frequency with a "Mode" switch control. The chip has been implemented using $0.18{\mu}m$ CMOS process. Measured results show the circuit exhibits peak-to-peak jitters of 37ps(@2.7Gbps) and 27ps(@1.62Gbps) in the recovered data. The power dissipation is 80mW at 2.7Gbps rate from a 1.8V supply.