• International journal of advanced smart convergence
• /
• v.10 no.1
• /
• pp.12-23
• /
• 2021

This paper proposes a low power radio frequency receiver front-end where, in a single stage, single-balanced mixer and voltage-controlled oscillator are stacked on top of low noise amplifier and re-use the dc current to reduce the power consumption. In the proposed topology, the voltage-controlled oscillator itself plays the dual role of oscillator and mixer by exploiting a series inductor-capacitor network. Using a 65 nm complementary metal oxide semiconductor technology, the proposed radio frequency front-end is designed and simulated. Oscillating at around 2.4 GHz frequency band, the voltage-controlled oscillator of the proposed radio frequency front-end achieves the phase noise of -72 dBc/Hz, -93 dBc/Hz, and -113 dBc/Hz at 10KHz, 100KHz, and 1 MHz offset frequency, respectively. The simulated voltage conversion gain is about 25 dB. The double-side band noise figure is -14.2 dB, -8.8 dB, and -7.3 dB at 100 KHz, 1 MHz and 10 MHz offset. The radio frequency front-end consumes only 96 ㎼ dc power from a 1-V supply.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.60 no.4
• /
• pp.871-876
• /
• 2011

In this paper, a voltage-controlled frequency tunable current-mode integrator and a 3rd-order current-mode Chebyshev filter in 1.8V-$0.18{\mu}m$ CMOS is realized for software radio applications in system-on-chips. This filter is used for reconstruction purposes between a current-steering DAC and a current-mode mixer. Power consumption of the designed filter can be reduced by using a current-mode small size integrator. And also, cutoff frequency of this filter is variable between 1.2MHz and 10.1MHz, the power consumption is 2.85mW. And the voltage bias compensated circuit is used to control the voltage variation.in the designed filter.

• Proceedings of the KIEE Conference
• /
• 1998.07b
• /
• pp.585-587
• /
• 1998

It is suggested that the PWM inverter is controlled by Digital Software Programming. VVVF(Variable Voltage Variable Frequency) inverter control being used by PWM control for driving the motor with speed-varying, makes the PWM pattern with calculating the output voltage and frequency, and with controlling the carrier and signal, so actually this method is difficult to correspond with driving the motor by using voltage-varying and frequency-varying. Therefore this research suggested the new algorithm controlled by micro processor which is already stored by various PWM form of output voltage by using fundamental data of the carrier and signal. The PWM wave can be controlled with real time by using extra hardware and digital software and to speed up program processing, the control signals to switch the power semi-conductor of three phase PWM inverter, simultaneously use the output signal by microprocessor and extra hardware, and control signal by software. In the end, this method was proved by applying to Three Phase Voltage-type Inverter.

• Proceedings of the KIEE Conference
• /
• 1998.07f
• /
• pp.2148-2150
• /
• 1998

This paper proposes a constant frequency controlled zero voltage switching method that can reduce switching losses caused by emf on inductance in DC motor. The zero voltage switching method is used more than a zero current switching method because of reducing switching losses by capacitance of depletion region of MOSFET. To simplify the controller circuit, we propose constant frequency controlled zero voltage switching method in the paper. The control method is more stable than a variable frequency control method because it can optimize bandwidth of a closed-loop and reactances. Therefore, we construct a constant frequency controlled zero voltage switching converter and improve zero switching losses in high switching frequency. In the process, we can control low-losses in full range on variable voltage and load. We simulate the proposed converter with P-SPICE and compare results obtained through the experiment.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.1
• /
• pp.131-137
• /
• 2014

A 120 GHz voltage controlled oscillator (VCO) with a divider chain including an injection locked frequency divider (ILFD) and six static frequency dividers is demonstrated using 65-nm CMOS technology. The VCO is designed based on the LC cross-coupled push-push structure and operates around 120 GHz. The 60 GHz ILFD at the first stage of the frequency divider chain is based on a similar topology as the core of the VCO to ensure the frequency alignment between the two circuit blocks. The static divider chain is composed of D-flip flops, providing a 64 division ratio. The entire circuit consumes a DC power of 68.5 mW with the chip size of $1385{\times}835{\mu}m^2$.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.6 no.6
• /
• pp.891-896
• /
• 2002

In this paper, a new voltage-controlled tunable integrator for low-voltage applications is proposed. The proposed active element is composed of the CMOS complementary cascode circuit which can extend transconductance of an element. Therefore, the unity gain frequency which is determined transcon-ductance is increased than that of the conventional element. And then these results are verified by the $0.25{\mu}m$ CMOS n-well parameter HSPICE simulation. As a result, the gain and the unity gain frequency are 42dB and 200MHz respectively in the element on 2V supply voltage. And power dissipation of the designed circuit is 0.32mW.

• Journal of the Korea Institute of Military Science and Technology
• /
• v.8 no.3 s.22
• /
• pp.64-72
• /
• 2005

In this paper, we propose a design method of the millimeter-wave(W-Band) waveguide cavity harmonic voltage controlled oscillator(VCO) using a Gunn diode for the armor sensor. Using the 3-dimensional simulation tool(Ansoft $HFSS^{TM}$), we were able to find the impedance matching point between waveguide and Gunn diode and estimate the oscillation frequency. A varactor diode is used for the frequency tuning, and we find out the equation for the calculation of the tunable frequency range. The designed VCO shows good performances; 17dBm output power at 94GHz center frequency, 520MHz frequency tuning range similar to the estimated value(480MHz).

• Journal of information and communication convergence engineering
• /
• v.6 no.3
• /
• pp.275-278
• /
• 2008

In this paper, I propose the full CMOS FLL(frequency locked loop) circuit. The proposed FLL circuit has a simple structure which contains a FVC(frequency-to-voltage converter), an operational amplifier and a VCO(voltage controlled oscillator). The operation of FLL circuit is based on frequency comparison by the two FVC circuit blocks. The locking time of FLL is short compared to PLL(phase locked loop) circuit because the output signal of FLL is synchronized only in frequency. The circuit is designed by 0.35${\mu}m$ process and simulation carried out with HSPICE. Simulation results are shown to illustrate the performance of the proposed FLL circuit.

• Proceedings of the KIEE Conference
• /
• 1988.11a
• /
• pp.341-344
• /
• 1988

This paper derives a condition foe constant voltage i constant frequency generation of doubly-fed induction generator. The condition is varied by the magnitude of output voltage, load current and its power factor, slip of the machine. Magnitude of output voltage is controlled by exiting voltage which is caculated by derived equation from operating condition. frequency of output voltage is controlled by injecting slip frequency to the rotor which is the difference between wanted output frequency and rotor frequency.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.11 no.10
• /
• pp.3905-3910
• /
• 2010

In this paper, a 3rd-order Chebyshev current-mode filter in 1.8V-$0.18{\mu}m$ CMOS parameter is designed. The core circuit of the current-mode filter is composed with the proposed voltage-controlled frequency tunable current-mode integrator. Using the proposed current-mode integrator, the cutoff frequency of the filter can be controlled and also total power consumption can be reduced. HSPICE simulation results show the cutoff frequency of the filter is controlled between 1.2MHz and 10.1MHz, and the power consumption is 2.85mW at Vdd=1.8V.