• Journal of Power Electronics
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• 제14권3호
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• pp.488-498
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• 2014

This paper presents an implementation of selective harmonic elimination (SHE) modulation for a single-phase 13-level transistor-clamped H-bridge (TCHB) based cascaded multilevel inverter. To determine the optimum switching angle of the SHE equations, the Newton-Raphson method is used in solving the transcendental equation describing the fundamental and harmonic components. The proposed SHE scheme used the relationship between the angles and a sinusoidal reference waveform based on voltage-angle equal criteria. The proposed SHE scheme is evaluated through simulation and experimental results. The digital modulator based-SHE scheme using a field-programmable gate array (FPGA) is described and has been implemented on an Altera DE2 board. The proposed SHE is efficient in eliminating the $3^{rd}$, $5^{th}$, $7^{th}$, $9^{th}$ and $11^{th}$ order harmonics, which validates the analytical results. From the results, it can be seen that the adopted 13-level inverter produces a higher quality with a better harmonic profile and sinusoidal shape of the stepped output waveform.

• 전력전자학회논문지
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• 제15권4호
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• pp.288-295
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• 2010

멀티레벨 인버터는 대용량 전력변환 분야의 요구를 만족하면서 파형왜곡을 감소시켜 전력품질 향상시킬 수 있으므로 근래에 상당히 주목받고 있다. 그런데 전압레벨이 증가함에 따라 복잡한 PWM 알고리즘을 구현하는데 FPGA가 적합하다. 본 논문에서는 FPGA로 5-레벨 다이오드 클램핑형 멀티레벨 인버터의 PWM 신호발생 기법을 제시한다. 유도전동기 제어용 DSP와 FPGA사이에 3상 기준전압 값을 안정되게 전송하는 기법을 제시한다. 32-비트 DSP와 cyclone-III FPGA를 사용한 실험 및 시뮬레이션을 통하여 반송신호 발생 방법으로 PWM 신호를 발생시키는 기법의 타당성을 검증한다.

• 전력전자학회논문지
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• 제22권6호
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• pp.469-475
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• 2017

Using impedance matching techniques as a way to increase system power transferability in capacitive wireless power transmission has been widely investigated in conventional studies. However, these techniques tend to increase the circuit volume and thus counterbalance the advantage of the simplicity in the energy link structure. In this paper, a compact circuit topology with one leakage-enhanced transformer is proposed in order to minimize the circuit volume for the capacitive power transfer system. This topology achieves a reactive compensation, and the system quality factor value can be reduced by the turn ratio. As a result, this topology not only reduces the overall system volume but also minimizes the voltage stress of the link capacitor. An optimal design guideline for the leakage-enhanced transformer is also presented. The advantages of the proposed scheme over the conventional method in terms of power efficiency and circuit volume are revealed through an analytic comparison. The feasibility of applying the new topology is also verified by conducting 50 W hardware tests.

• 한국표면공학회지
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• 제50권2호
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• pp.108-113
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• 2017

We investigated the effect of graphite electrode geometry and combination on nanocarbon material synthesis using underwater discharge plasma(UDP). The UDP system consists of two graphite electrodes and beaker filled with de-ionized water. A high voltage of 15 kV with a frequency of 25 kHz is applied to produce UDP using an alternating-current power source. The UDP system with conical electrodes produced the largest amount of products due to the concentration of electrical fields between electrodes. In addition, hollow-shaped stationary electrode and conical-shaped moving electrode stores discharge-induced bubbles and maintains longer reaction time. We found from Raman spectroscopy and electron microscopy that high quality carbon nanomaterials including carbon nanotubes are synthesized by the UDP system.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 하계학술대회 논문집 D
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• pp.2717-2719
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• 2003

In this paper, we developed an efficient virtual experiment kit with creative and interactive multimedia contents, which can be used to enhance the quality of education in the area of digital logic circuits. Since our virtual experiment kit is implemented to describe the on-campus laboratory, the learners can obtain similar experimental data through it. Also, our web-based virtual experiment kit is designed to enhance the efficiency of both the learners and the educators. The learners will be able to achieve high learning standard and the educators save time and labor. The virtual experiment is performed according to the following procedure: (1) Circuit Composition on the Bread Board (2) Applying Input Voltage (3) Output Measurements (4) Checkout of Experiment Results. Furthermore, the circuit composition on the bread board and its corresponding online schematic diagram are displayed together on the virtual experiment kit for the learner's convenience. Finally, we have obtained several affirmative effects such as reducing the total experimental hours and the damage rate for experimental equipments and increasing learning efficiencies as well as faculty productivity.

• 전기학회논문지
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• 제63권10호
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• pp.1461-1466
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• 2014

GIS(Gas Insulated Switchgear) is important power apparatus which have strong dielectric strength, supply electric power and is a part of the power system. Most substation type is configured as GIS. Recently, because of continuous increasement of GIS demand resulted from high quality & big capacity of electric power, the necessity of the preventive & diagnosis system is being expanded gradually. GIS partial discharge occurred on the UHF band is detected effectively by the method to IEC 60270 that recommend to be able to detect the apparent minimum discharge, 5 pC. Additionally, the UHF sensor should be installed to detect PD signal if Partial discharge signal, 5 pC occur in every part of GIS. Currently PD diagnosis system applying UHF sensor for GIS with various voltage level like 154 kV, 345 kV, 765 kV have been operated. And it is necessary to measure and analyze insulation breakdown phenomenon of inside GIS exactly. In this paper, we proposed Fat-dipole patch UHF sensor that is developed and more sensitive, excellent wide-range characteristic than the exising UHF sensor. And we performed KERI (Korea Electrotechnology Research Institute) reference test, which showed the excellent result for the all tests.

• 전기학회논문지
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• 제67권6호
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• pp.715-723
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• 2018

The energy storage system consists of batteries, power conditioning system and energy management system. If ESS is installed and operated in the field, SAT(Site Acceptance Test) of ESS is being essentially required for the safety and performance of ESS. Furthermore, in order to more accurately and reliably validate the performance of the ESS in advanced countries, it has been required to perform not only performance testing by H/W equipments but also performance verification by S/W tool. Therefore, this paper proposes the modeling of portable test equipment in order to evaluate the performance and reliability of ESS by using the PSCAD/EMTDC S/W. And also, the prototype of 30[kW] scaled portable test equipments is implemented based on the S/W modeling. From the results of various simulations and testings such as power quality, LVRT and anti-islanding tests, it is confirmed that 30[kW] scaled portable test equipment is useful for SAT of ESS, because the simulation results of PSCAD/EMTDC are identical to them of 30[kW] test equipment at the same test conditions.

• Journal of Power Electronics
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• 제15권2호
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• pp.356-365
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• 2015

This paper presents a new single phase front-end ac-dc bridgeless power factor correction (PFC) rectifier topology. The proposed converter achieves a high efficiency over a wide range of input and output voltages, a high power factor, low line current harmonics and both step up and step down voltage conversions. This topology is based on a non-inverting buck-boost (Zeta) converter. In this approach, the input diode bridge is removed and a maximum of one diode conducts in a complete switching period. This reduces the conduction losses and the thermal stresses on the switches when compare to existing PFC topologies. Inherent power factor correction is achieved by operating the converter in the discontinuous conduction mode (DCM) which leads to a simplified control circuit. The characteristics of the proposed design, principles of operation, steady state operation analysis, and control structure are described in this paper. An experimental prototype has been built to demonstrate the feasibility of the new converter. Simulation and experimental results are provided to verify the improved power quality at the AC mains and the lower conduction losses of the converter.

• Journal of Power Electronics
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• 제13권6호
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• pp.1058-1069
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• 2013

This paper proposes and designs a new output filter called an LCFL filter for application to three phase three wire shunt active power filters (SAPF). This LCFL filter is derived from a traditional LCL filter by replacing its capacitor with a C-type filter, and then constructing an L-C-type Filter-L (LCFL) topology. The LCFL filter can provide better switching ripple attenuation capability than traditional passive damped LCL filters. The LC branch series resonant frequency of the LCFL filter is set at the switching frequency, which can bypass most of the switching harmonic current generated by a SAPF converter. As a result, the power losses in the damping resistor of the LCFL filter can be reduced when compared to traditional passive damped LCL filters. The principle and parameter design of the LCFL filter are presented in this paper, as well as a comparison to traditional passive damped LCL filters. Simulation and experimental results are presented to validate the theoretical analyses and effectiveness of the LCFL filter.

• Journal of Power Electronics
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• 제17권3호
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• pp.686-694
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• 2017

Due to the wide use of electronic products, digitally controlled DC-DC converters are attracting more and more attention in recent years. However, digital control strategies may introduce undesirable Limit Cycle Oscillation (LCO) due to quantization effects in the Analog-to-Digital Converter (ADC) and Digital Pulse Width Modulator (DPWM). This results in decreases in the quality of the output voltage and the efficiency of the system. Meanwhile, even if the resolution of the DPWM is finer than that of the ADC, LCO may still exist due to improper parameters of the digital compensator. In order to discover how LCO is generated, the state space averaging model is applied to derive equilibrium equations of a digital PID controlled DC-DC converter in this paper. Furthermore, the influences of the parameters of the digital PID compensator, and the resolutions of the ADC and DPWM on LCO are studied in detail. The amplitude together with the period of LCO as well as the corresponding PID parameters are obtained. Finally, MATLAB/Simulink simulations and FPGA verifications are carried out and no-LCO conditions are obtained.