• Journal of Electrical Engineering and Technology
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• 제10권1호
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• pp.261-270
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• 2015

In this paper, the Optimal Harmonic Stepped Waveform (OHSW) method is proposed in order to eliminate the selective harmonic orders available at the output of cascaded multilevel inverter (CMLI) fed by solar photovoltaic (SPV). This technique is used to solve the harmonic elimination equations based on stepped waveform analysis in order to obtain the optimal switching angles which in turn reduce the Total Harmonic Distortion (THD). The OHSW method considers the output voltage waveform as four equal symmetries in each half cycle. In the proposed method, a solar fed fifteen level cascaded multilevel is considered where the magnitude of six numbers of harmonic orders is reduced. A programmable pulse generator is developed to carry the switching angles directly to the semiconductor switches obtained as a result of OHSW analysis. Simulations are carried out in MATLAB/Simulink in which a separate model is developed for solar photovoltaic which serves as the input for cascaded multilevel inverter. A 3kWp solar plant with multilevel inverter system is implemented in hardware to show the effectiveness of the proposed system. Based on the observation the OHSW method provides the reduced THD thereby improving power quality in renewable energy applications.

• Transactions on Electrical and Electronic Materials
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• 제13권2호
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• pp.78-84
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• 2012

An in-situ optical monitoring method for real-time process monitoring of electrochemical copper deposition (CED) is presented. Process variables to be controlled in achieving desired process results are numerous in the CED process, and the importance of the chemical bath conditions cannot be overemphasized for a successful process. Conventional monitoring of the chemical solution for CED relies on the pH value of the solution, electrical voltage level for the reduction of metal cations, and gravity measurement by immersing sensors into a plating bath. We propose a nonintrusive optical monitoring technique using three types of optical sensors such as chromatic sensors and UV/VIS spectroscopy sensors as potential candidates as a feasible optical monitoring method. By monitoring the color of the plating solution in the bath, we revealed that optically acquired information is strongly related to the thickness of the deposited copper on the wafers, and that the chromatic information is inversely proportional to the ratio of $Cu$ (111) and {$Cu$ (111)+$Cu$ (200)}, which can used to measure the quality of the chemical solution for electrochemical copper deposition in advanced interconnection technology.

• 한국전기전자재료학회논문지
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• 제25권12호
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• pp.1009-1014
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• 2012

Hydrogenated amorphous silicon (${\alpha}$-Si:H) layers deposited by plasma enhanced chemical vapor deposition (PECVD) are investigated for use in silicon hetero-junction solar cells employing n-type crystalline silicon (c-Si) substrates. The optical and structural properties of silicon hetero-junction devices have been characterized using spectroscopy ellipsometry and high resolution cross-sectional transmission electron micrograph (HRTEM). In addition, the effective carrier lifetime is measured by the quasi-steady-state photocoductance (QSSPC) method. We have studied on the correlation between the order of ${\alpha}$-Si:H and the passivation quality at the interface of ${\alpha}$-Si:H/c-Si. Base on the result, we have fabricated a silicon hetero-junction solar cell incorporating the ${\alpha}$-Si:H passivation layer with on open circuit voltage ($V_{oc}$) of 637 mV.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2010년도 춘계학술대회 초록집
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• pp.99.2-99.2
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• 2010

This paper investigates the dependence of a-Si:H/c-Si passivation and heterojunction solar cell performances on various cleaning processes of silicon wafer and surface morphology. It is observed that passivation quality of a-Si:H thin-films on c-Si wafer highly depends on wafer surface conditions. The MCLT(Minority carrier life time) of wafer incorporating intrinsic (i) a-Si:H as a passivation layer shows sensitive variation with cleaning process and surface morpholgy. By applying improved cleaning processes and surface morphology we can obtain the MCLT of $200{\mu}sec$ after H-termination and above 1.5msec after i a-Si:H thin film deposition, which has implied open circuit voltage of 0.720V.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.186-186
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• 2012

This report investigates a new synthetic route and the size-dependent optical and electrical properties of PbS nanocrystal quantum dots (NQDs) in diameters ranging between 1.5 and 6 nm. Particularly we synthesize ultra-small sized PbS NQDs having extreme quantum confinement with 1.5~2.9 nm in diameter (2.58~1.5 eV in first exciton energy) for the first time by adjusting growth temperature and growth time. In this region, the Stokes shift increases as decreasing size, which is testimony to the highly quantum confinement effect of ultra-small sized PbS NQDs. To find out the electrical properties, we fabricate self-assembled films of PbS NQDs using layer by layer (LBL) spin-coating method and replacing the original ligands with oleic acid to short ligands with 1, 2-ethandithiol (EDT) in the course. The use of capping ligands (EDT) allows us to achieve effective electrical transport in the arrays of solution processed PbS NQDs. These high-quality films apply to Schottky solar cell made in an glass/ITO/PbS/LiF/Al structure and thin-film transistor varying the PbS NQDs diameter 1.5~6 nm. We achieve the highest open-circuit voltage (＜0.6 V) in Schottky solar cell ever using PbS NQDs with first exciton energy 2.58 eV.

• 제어로봇시스템학회논문지
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• 제11권6호
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• pp.558-563
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• 2005

In this paper, we implemented a web-based virtual laboratory system(VLab system) with creative and interactive multimedia contents, which can be used to enhance the quality of education in the area of digital logic circuits. Since the proposed VLab system is implemented to describe the on-campus laboratory, the learners can obtain similar experimental data through it. Also, the VLab system is designed to increase the learning and teaching efficiencies of both the learners and the educators, respectively. The learners will be able to achieve high teaming standard and the educators save their time and labor. The virtual experiments on our VLab system are performed according to the following procedure: (1) Circuit composition on the virtual bread board (2). Applying input voltage (3) Output measurements (4) Checkout of experiment results. Furthermore, the circuit composition on the virtual bread board and its corresponding online schematic diagram are displayed together on the VLab system for the learner's convenience. Finally, we have obtained several affirmative effects such as reducing the total experimental hours and the damage rate for experimental equipments and increasing learning efficiencies as well as faculty productivity.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(1)
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• pp.213-216
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• 2004

This paper describes design and implementation of the 5.5 GHz VCO with parallel-branch inductors using 0.8${\mu}m$ SiGe HBT process technology. The proposed parallel-branch inductor shows $12 \%$ improvement in quality factor in comparison with the conventional inductor. A phase noise of -93 dBc/Hz is measured at 100 kHz offset frequency, and the harmonics in the VCO are suppressed less than -23 dBc. The single-sided output power of the VCO is -6.5$\pm$1.5 dBm. The manufactured VCO consumes 15.0 mA with 2.5 V supply voltage. Its chip areas are 1.8mm ${\times}$ 1.2mm.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.155-158
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• 2005

An invesitigation on power consumption of a mobile multimedia system using OFDM and MDVS technique is reported here. Analysis and simulation are performed to find the significances of proposed Microscopic Dynamic Voltage Scaling(MDVS) tehnique[4] on digital processor in terms of power saving. A study is also made to show power reduction in mobile multimedia system by incorporating OFDM modulation scheme in RF front-end. Finally, overall power consumption by functionally distinguished blocks ie. RF front-end, digital processor and human interface unit is shown here. Total power consumption is 8.2W for 2Mbps SD-quality WCDMA multimedia video service - the power consumption of digital processor is 3.9W(48%), the power consumption of RF front-end is 3.2W (36%), and the power consumption of interface is 1.8W(16%). Power saving of applying purposed MDVS technique is 35% in digital processor, and power saving of OFDM technique is 10-12dB in RF front-end.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.797-800
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• 2005

In this paper, the designed 10-bit current steering data driving circuit consists of bias circuits, shift registers, data and line latches, level shifters, and 10-bit D/A converters. This data driving circuit can improve image quality, driving speed, and can reduce process error, DNL error, and glitch noise. To reduce current cells, the 10-bit D/A converter was designed 3+3+4 hybrid type. As a result 49 current cells are decreased. The transient analysis shows that currents flows a few of mA in data line and the currents have 1024 gray levels of current values. Total circuits are designed for 10 ${\mu}s$ speed. Thus the designed 10-bit current steering data driving circuit can be usable in HDTV/XGA AMOLED displays. These data driving circuits are designed for 0.35 ${\mu}m$ CMOS process at 3.3 V and 18 V supply voltage and simulated with HSPICE..

• 한국결정성장학회지
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• 제14권3호
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• pp.90-94
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• 2004

The variation of electrical properties of (Ba,Sr)$TiO_3$ [BST] thin films for Metal-Insulator-Semiconductor (MIS) capacitors was investigated. BST thin films were deposited on p-Si(100) substrates by the RF magnetron sputtering with temperature range of 500~$600^{\circ}C$. The dielectric properties of MIS capacitors consisting of AUBST/$SiO_2$/Si sandwich structure were measured for various conditions. We examined the characteristics of MIS capacitor with various oxygen pressure, substrate temperature and (Ba+Sr)/Ti ratio. It was found that the leakage current was reduced in MIS capacitor with high quality $SiO_2$ layer was grown on bare p-Si substrate by thermal oxidation. The BST MIS structure showed relatively high capacitance even though it is the combination of high-dielectric BST thin films and $SiO_2$ layer. The charge state densities of the MIS capacitors and Current-voltage characteristics of the MIS capacitor were investigated. By applying $SiO_2$ layer between BST thin films and Si substrate, low leakage current of $10^{-10}$ order was observed.