• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.7 s.337
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• pp.27-36
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• 2005

This paper presents an area-efficient architecture to implement the high-speed Reed-Solomon(RS) decoder, which is used in a variety of communication systems such as wireless and very high-speed optical communications. We present the new pipelined-recursive Modified Euclidean(PrME) architecture to achieve high-throughput rate and reducing hardware-complexity using folding technique. The proposed pipelined recursive architecture can reduce the hardware complexity about 80$\%$ compared to the conventional systolic-array and fully-parallel architecture. The proposed RS decoder has been designed and implemented with the 0.13um CMOS technology in a supply voltage of 1.2 V. The result show that total number of gate is 393 K and it has a data processing rate of S Gbits/s at clock frequency of 625 MHz. The proposed area-efficient architecture can be readily applied to the next generation FEC devices for high-speed optical communications as well as wireless communications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.46-53
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• 2011

This paper presents an equalizer reducing CCI(cell-to-cell interference) in MLC NAND flash memory. The CCI is a critical factor which affects occurring data errors in a cell, when surrounding cells are programed. We derived a characteristic equation for CCI considering write procedure of data that is similar with signal equalizing. The model considers the floating gate capacitance coupling effect, the direct field effect, and programming methods of the MLC NAND flash memory. We verify the proposed equalizer comparing with the measured data of 1-block MLC NAND flash memory. As the simulation result, the equalizer shows an error correction ratio about 60% under 20nm NAND process.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.592-595
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• 2008

This paper presents development of automatic image quality register optimization system using mobile TFT-LCD (Thin Film Transistor-Liquid Crystal Display) driver IC and embedded software. It optimizes automatically gamma adjustment and voltage setting registers in mobile TFT-LCD driver IC to improve gamma correction error, adjusting time, flicker noise and contrast ratio. Developed algorithms and embedded software are generally applicable for most of the TFT-LCD modules. The proposed optimization system contains module-under-test (MUT, TFT-LCD module), control program, multimedia display tester for measuring luminance, flicker noise and contrast ratio, and control board for interface between PC and TFT-LCD module. The control board is designed with DSP and FPGA, and it supports various interfaces such as RGB and CPU.

• Journal of Power Electronics
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• v.17 no.4
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• pp.1048-1057
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• 2017

An indirect matrix converter (IMC) is a modern power generation system that enables a direct ac/ac conversion without the need for any bulky and limited lifetime electrolytic capacitor. This system also allows four-quadrant operation, generation of sinusoidal output voltage waveforms with variable frequency and amplitude, and control of input power factor. This study proposes a pulse-width modulation-based sliding-mode controller to achieve unity input-power factor operation of the IMC independently of the active power exchanged with the grid, as well as a fast dynamic response. The designed equivalent control law determines, at each sampling period, the appropriate q-axis component of the modulated input current to be injected into the grid through the LC input filter. An integral term of the error is included in the expression of the sliding surface to increase the accuracy of the control method. A double space vector modulation method is used to synthesize the direction of the space vector of the input currents as required by the sliding-mode controller and the space vectors of the target output voltages. Simulation and experimental results are provided to show the effectiveness and evaluate the performance of the proposed control method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.118-124
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• 2008

For forward error correction, DVB-S2, which is the digital video broadcasting forward error coding and modulation standard for satellite television, uses a system based the concatenation of BCH with LDPC inner coding. In DVB-S2 the LDPC codes are defined for 11 different code rates, which means that a DVB-S2 LDPC decoder should support multiple code rates. Seven of the 11 code rates, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10, are regular and the rest four code rates, 1/4, 1/3, 2/5, and 1/2, are irregular. In this paper we propose a flexible decoder for the regular LDPC codes. We combined the partially parallel decoding architecture that has the advantages in the chip size, the memory efficiency, and the processing rate with Benes network to implement a DVB-S2 LDPC decoder that can support multiple code rates with a block size of 64,800 and can configure the interconnection between the variable nodes and the check nodes according to the parity-check matrix. The proposed decoder runs correctly at the frequency of 200MHz enabling 193.2Mbps decoding throughput. The area of the proposed decoder is $16.261m^2$ and the power dissipation is 198mW at a power supply voltage of 1.5V.