• 전기학회논문지
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• 제60권4호
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• pp.781-788
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• 2011

This paper proposes a boost-input self-driven active clamp ZVS converter eliminating the extra dirve circuit for the active clamp switch. The converter used the auxiliary winding of the transformer to drive the active clamp switch and to achieve asymmetrical duty control. This paper presents the operation principle and the analyzed results of dynamic characteristics including steady state characteristics of the converter proposed. The experimental results were used to verify the theoretical predictions. A 300W (15V/20A) prototype converter that only exhibited 2-turn winding number in the auxiliary winding was sufficient to drive the active clamp switch on the input voltage of 80V. Finally, the maximum efficiency of 91.2% was achieved for the prototype converter and the proposed converter had stable closed loop characteristic with phase margin $55^{\circ}$.

• Journal of Power Electronics
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• 제2권3호
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• pp.199-205
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• 2002

This paper compares three kinds of soft-switching circuits from viewpoints of surge suppression, load characteristic, and power efficiency for a tapped-inductor buck converter with low voltage and high current. As a result, these soft-switching techniques have achieved much higher efficiency of 80 % when compared with a hard-switching buck converter for the output condition of 1V and 20A.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.301-303
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• 2001

This paper proposes the boost input type active clamp DC-DC converter featuring the high efficiency and improved EMI characteristics. The main characteristic of the converter is to operate with the non-pulsating input and output currents. Besides, it has the zero-voltage switching (ZVS) and low voltage stress characteristics. For the proposed converter, the detailed operation principles and the simulation results are presented.

• 대한전자공학회논문지SD
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• 제45권10호
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• pp.1-6
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• 2008

고전압 MOSFET에서 스냅백 이후의 유지 전압은 구동전압에 비해 매우 작아서 고전압 MOSFET이 파워 클램프로 바로 사용될 경우 래치업 문제를 일으킬 수 있다. 본 연구에서는 Drain-Extended PMOS를 이용하여 래치업 문제가 일어나지 않는 구조를 제안하였다. 제안된 구조에서는 래치업의 위험을 피하기 위해 소자가 스냅백이 일어나지 않는 영역으로 동작 영역을 제한하였다. $0.35\;{\mu}m$ 60V BCD(Bipolar-CMOS-DMOS) 공정을 사용하여 제작된 칩을 측정한 결과를 통해 제안된 기존의 gate-driven 구조의 LDMOS(Lateral Double-Diffused MOS)를 사용한 ESD 파워 클램프에 비해 500% 성능향상(강인성)이 있게 된 것을 알 수 있다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2014년도 전력전자학술대회 논문집
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• pp.403-404
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• 2014

전기 자동차 및 하이브리드 자동차는 차량의 12V 부하에 전원을 공급하고 12V 배터리를 충전시키기 위해 DC/DC 컨버터를 사용한다. 이 DC/DC컨버터를 LDC(Low voltage DC/DC Converter)라 한다. 본 논문에서는 Active Clamp 방식의 포워드 컨버터를 이용하여 소용량 LDC를 개발한 내용을 소개 하였다.

• The Korean Journal of Physiology
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• 제25권2호
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• pp.125-131
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• 1991

Inactivation properties of Ca current in the unfertilized eggs of mouse were studied by using the whole cell voltage clamp technique and single microelectrode voltage clamp technique. Membrane potential was held at -80 mV and step depolarization was applied from -50 mV to 50 mV for $200{\sim}500\;ms$. Peak of inward Ca currents was $-2{\sim}-4\;nA$ at a membrane Potentials from -20 mV to 0 mV and outward currents were not observed within the membrane voltage range studied $(-50{\sim}50\;mV)$. Inward currents were fully inactivated within 200 ms after the onset of step depolarization. As the membrane became depolarized, time constant of inactivation (${\tau}$) was decreased but remained around $20{\sim}30\;ms$ beyond 10 mV. When $Ca^{2+}$ was used as a charge earlier, inactivation of inward $Ca^{2+}$ current also occured and time course of inactivation was similar to that of $Ca^{2+}$ currents as charge carrier. In the bathing solution containing high potassium $(131\;mM\;K^+)$, process of inactivation was not changed except a parallel decrease of value for the entire range of membrane potential. Steady-state inactivation of the $current(h_{\infty})$ obtained from the double pulse experiment showed the voltage-dependent change. These results suggested that inactivation of Ca currents in the unfertilized eggs of mouse was voltage-dependent.

• 전기전자학회논문지
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• 제18권1호
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• pp.25-30
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• 2014

본 논문에서는 파워 클램프에 적용하기 위한 SCR 기반의 ESD 보호회로를 제안하였다. 기존 SCR 구조의 낮은 홀딩 전압에 의한 래치-업 문제를 개선하기 위해 n+ 플로팅 영역을 삽입하고 추가적인 n-웰과 p-웰까지 확장된 p+ 캐소드 영역을 통해 높은 홀딩 전압을 가질 수 있도록 고안되었다. 제안된 ESD 보호회로는 높은 홀딩 전압을 통해 정상 동작 상태에서의 래치-업 면역 특성을 확보하였으며, 우수한 ESD 보호 능력을 가진다. 제안된 ESD 보호회로는 Synopsys사의 TCAD 시뮬레이션을 통해 전기적 특성을 검증하였다. 시뮬레이션 결과, 트리거 전압은 약 27.3 V에서 최대 32.71 V 사이에서 변화하는 반면, 홀딩 전압은 4.61 V에서 최대 8.75 V까지 상승하는 것을 확인하였다. 따라서 제안된 ESD 보호회로는 트리거 전압은 기존 SCR과 비슷한 수준을 유지하면서 높은 홀딩 전압을 갖는다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 A
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• pp.453-457
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• 1996

DC/DC converter is widely used in computer, electronic communication and industrial apparatus where the regulated dc supply is needed. FB-ZVS converter is suitable for high-power, high-frequency and constant frequency control. Because the voltage stress of the diode rectifier is high due to the ring effect, the clamp circuit is essential to reduce the voltage stress. The nondissipative active clamp circuit eliminates ring effect. Analysis of FB-ZVS converter and the validity of the active clamp circuit are studied through the simulation, and the experimental results show the superior characterics of the proposed system.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.1309_1310
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• 2009

The topology of active clamp forward converter provides ZVS characteristic and also the stress of voltage and current is smaller than that of the conventional forward converters. The benefits of this technique include a higher efficiency at a high switching frequency, lower EMI/RFI. In this paper, the active clamp forward converter is designed for operation in wide range voltage and has 19.5V/120W ratings with efficiency more than 90%.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 B
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• pp.1005-1008
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• 2001

This paper presents average current-mode control AC/DC ZVT(Zero Voltage Transition) Boost Converter. This boost converter perceives feed forward signal of input and feedback signal of output for average current-mode control proposed converter employs active-clamp method for ZVT. This converter gives the good PFC(Power Factor Correction), low line current hormonic distortions and tight output voltage regulations. This converter also has a high efficiency by active-clamp method. The principle of operation, feature, and design considerations are illustrated and verified through the experiment with a 150W, 120kHz prototype converter.