• The Transactions of the Korean Institute of Power Electronics
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• v.11 no.5
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• pp.395-403
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• 2006

This paper has proposed a new dead time compensation method for a voltage-fed PMW inverter. In the voltage-fed PMW inverter, a voltage distortion is generated by the dead time effect and the nonlinear characteristics of the switching devices. Especially, the distorted voltage causes 5th and 7th harmonics in the stationary phase currents, and 6th harmonic in the synchronous phase currents. As a result, the integrator output of the synchronous PI current regulator has the ripple corresponding to six times of the inverter output frequency. In this paper, the signal of the integrator output of the d-axis current regulator is used as the control signal for the dead time compensation. The experimental and simulation results are presented to verify the validity of the proposed method.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.59 no.2
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• pp.141-145
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• 2010

Most of the industrial loads includes the non-linear load as well as the linear load because there are many kinds of power conversion equipments at the input stage of the load in distribution network. The non-linear load causes the distortion of voltage waveform at PCC because the non-linear load generates the harmonic current. As a result, various voltage harmonics are existed at PCC depending on the current harmonics from the non-linear load. And, a series reactor is generally connected to the power capacitor in series to attenuate the distortion of voltage waveform and to reduce an inrush current of power capacitor. Also, harmonic current of power capacitor is highly dependent on the series reactor because it is operated with the power capacitor as a passive filter against nonlinear loads. Then, these capacitors might be damaged by the excessive voltage and current harmonic components. In this paper, we presented how to select the capacitor and series reactor to meet the requirement of the voltage distortion at PCC and analyzed the voltage, current and capacity rating of the power capacitor by the computer simulation to ensure the safe operation of power capacitor when the voltage harmonics at PCC are existed. Also, the analysis data were compared with the experimental measurements for the verification.

• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.5
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• pp.422-428
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• 2013

Recently, we use a static synchronous compensator(STATCOM) with cascaded H-bride topologies, because it is easy to increase capacity and to reduce total harmonic distortion(THD). When we use equipment for reactive power compensation, dc-link voltage unbalances occur from several reasons although loads are balanced. In the past, switching pattern change of single phase inverter and reference voltage magnitude change of inverter equipped with power sensor have been used for dc-link voltage balance. But previous methods are more complicated and expensive because of additional component costs. Therefore, this paper explains reasons of dc-link voltage unbalance and proposes solution. This solution is complex method that is composed of reference voltage magnitude change of inverter without additional hardware and shifted phase angle of inverter reference voltages change. It proves possibility through 1000[KVA] system simulation.

• Proceedings of the KIPE Conference
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• 2003.07a
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• pp.455-460
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• 2003

The a PWM VSI, the voltage distortion exists between the reference and output voltage. This distortion is caused by the intended blanking time and the inherent characteristics of the switching devices which are function of the operating condition. In this paper, the dead-time effects are analysed and a new on-line estimation method for a PMSM is proposed to compensate time varying dead-time effects

• Journal of Power Electronics
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• v.13 no.4
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• pp.712-718
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• 2013

This paper proposes a control method for reducing the total harmonic distortion (THD) of the grid current of three-phase grid-connected inverter systems when the grid voltage is distorted. The THD of the grid current caused by grid voltage harmonics is derived by considering the phase delay and magnitude attenuation due to the hardware low-pass filter (LPF). The Cauchy-Schwarz inequality theory is used in order to search more easily for the minimum point of the THD. Both the gain and angle of the compensation voltage at the minimum point of the THD of the grid current are derived with the variation of cut-off frequencies of the hardware LPF. Simulation and experimental results show the validity of the proposed control methods.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.425-428
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• 2000

A new dead time compensation method using time delay control approach is presented. The dead time in switching pattern cause the voltage distortion and it can be considered as the disturbance voltage. In this paper the disturbance voltage is estimated using time delay control and the estimated disturbance voltage is summed with voltage command in predictive current control by a feed-forward. The proposed scheme is implemented on a PMSM and the effectiveness is verified through comparative simulation.

• Journal of Power Electronics
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• v.18 no.6
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• pp.1889-1900
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• 2018

Harmonic current mitigation is vital in power distribution networks owing to the inflow of nonlinear loads, distributed generation, and renewable energy sources. The active power filter (APF) is the current electrical equipment that can dynamically compensate for harmonic distortion and eliminate asymmetrical loads. The compensation performance of an APF largely depends on the control strategy applied to the voltage source inverter (VSI). Model predictive control (MPC) has been demonstrated to be one of the effective control approaches to providing fast dynamic responses. This approach covers different types of power converters due to its several advantages, such as flexible control scheme and simple inclusion of nonlinearities and constraints within the controller design. In this study, a finite control set-MPC technique is proposed for the control of VSIs. Unlike conventional control methods, the proposed technique uses a discrete time model of the shunt APF to predict the future behavior of harmonic currents and determine the cost function so as to optimize current errors through the selection of appropriate switching states. The viability of this strategy in terms of harmonic mitigation is verified in MATLAB/Simulink. Experimental results show that MPC performs well in terms of reduced total harmonic distortion and is effective in APFs.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.11
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• pp.1560-1565
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• 2013

This paper proposes the control method for compensating for unbalanced grid current and reducing a total harmonic distortion (THD) of the grid current at the three-phase grid-connected inverter systems under unbalancd and distorted grid voltage conditions. The THD of the grid current caused by grid voltage harmonics is derived by considering the phase delay and magnitude attenuation due to the hardware low-pass filter (LPF). The Cauchy-Schwarz inequality theory is used in order to search more easily for a minimum point of THD. Both the gain and angle of a compensation voltage at the minimum point of THD of the grid current are derived. The negative-sequence components in the three-phase unbalanced grid voltage are cancelled in order to achieve the balanced grid current. The simulation and experimental results show the validity of the proposed control methods.

• Journal of Electrical Engineering and Technology
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• v.11 no.6
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• pp.1707-1713
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• 2016

This paper proposes a dc error compensation algorithm using dq-synchronous coordinate transform digital phase-locked-loop in single-phase grid-connected converters. The dc errors are caused by analog to digital conversion and grid voltage during measurement. If the dc offset error is included in the phase-locked-loop system, it can cause distortion in the grid angle estimation with phase-locked-loop. Accordingly, recent study has dealt with the integral technique using the synchronous reference frame phase-locked-loop method. However, dynamic response is slow because it requires to monitor one period of grid voltage. In this paper, the dc offset error compensation algorithm of the improved response characteristic is proposed by using the synchronous reference frame phase-locked-loop. The simulation and the experimental results are presented to demonstrate the effectiveness of the proposed dc offset error compensation algorithm.

• Journal of Power Electronics
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• v.19 no.6
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• pp.1380-1392
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• 2019

Input filters are very important to matrix converters (MCs). They are used to improve grid side current waveform quality and to reduce the input voltage distortion supplied to the grid side. Due to the effects of the input filter and the output power, the grid side power factor (PF) is not at unity when the input power factor angle is zero. In this paper, the displacement angle between the grid side phase current and the phase voltage affected by the input filter parameters and output power is analyzed. Based on this, a new grid side PF unity compensation method implemented in the indirect space vector pulse width modulation (ISVPWM) method is presented, which has a larger compensation angle than the traditional compensation method, showing a higher grid side PF at unity in a wide output power range. Simulation and experimental results verify that the analysis of the displacement angle between the grid side phase current and the phase voltage affected by the input filter and output power is right and that the proposed compensation method has a better grid side PF at unity.