• Journal of Korea Multimedia Society
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• v.10 no.8
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• pp.1060-1067
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• 2007

We need various methods to develop MMORPG that is game genre which many users use among various game genre using Internet. Specially, to heighten efficiency of distributing work, Object-oriented language such as C++ is used and we need design techniques that can take advantage of enough object-oriented concept when making large-scale game. There is various pattern that can apply in software breakup design in GoF's design pattern for these design techniques. If you apply Observer pattern to Party System Design for forming community between game users, you can easily add new class and maintain system later. Party Play is one of the important system that is used to form game users' community in MMORPG games. The main point that must be considered in Party-Play-System is to divide evenly experience value and acquisition that is got by Party-Play among users according to each user's level. To implement Party Play System that consider maintenance of system, in this paper, we propose a method using GoF's Observer-Pattern, showing you that proposed method which has advantage to dynamic memory allocation and to virtual method call can be used usefully to change object to real time at program run and to add new class and to maintain system new.

• The Transactions of the Korea Information Processing Society
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• v.4 no.3
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• pp.831-845
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• 1997

In this paper,we proposed and developed a compiler and interactive programming enviroments for C++ wich is mostly worth of nitice among the object -oriented languages.To develope the compiler for C++ we took front=end/back-end model using EM virtual machine.In develpoing Front-End,we formailized C++ gram-mar with the context semsitive tokens which must be manipulated by dexical scanner and designed a AST class li-brary which is the hierarchy of AST node class and well defined interface among them,In develpoing Bacik-End,we proposed model for three major components :code oprtimizer,code generator and run-time enviroments.We emphasized the retargatable back-end which can be systrmatically reconfigured to genrate code for a variety of distinct target computers.We also developed terr pattern matching algorithm and implemented target code gen-erator which produce SPARC code.We also proposed the theroy and model for construction interative pro-gramming enviroments. To represent language features we adopt AST as internal reprsentation and propose uncremental analysis algorithm and viseal digrams.We also studied unparsing scheme, visual diagram,graphical user interface to generate interactive environments automatically Results of our resarch will be very useful for developing a complier and programming environments, and also can be used in compilers for parallel and distributed enviroments.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.4
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• pp.274-279
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• 2009

The flow of a universal system-level design methodology consists of system specification, system-level hardware/software partitioning, co-design, co-verification using virtual or physical prototype, and system integration. In this paper, verification environments based-on SystemVerilog and SystemC, one is native-code co-verification environment which makes prompt functional verification possible and another is SystemVerilog layered testbench which makes clock-level verification possible, are implemented. In native-code co-verification, HW and SW parts of SoC are respectively designed with SystemVerilog and SystemC after HW/SW partitioning using SystemC, then the functional interaction between HW and SW parts is carried out as one simulation process. SystemVerilog layered testbench is a verification environment including corner case test of DUT through the randomly generated test-vector. We adopt SystemC to design a component of verification environment which has multiple inheritance, and we combine SystemC design unit with the SystemVerilog layered testbench using SystemVerilog DPI and ModelSim macro. As multiple inheritance is useful for creating class types that combine the properties of two or more class types, the design of verification environment adopting SystemC in this paper can increase the code reusability.

• The Journal of Korean Association of Computer Education
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• v.17 no.2
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• pp.65-76
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• 2014

This paper aims at implementing experimental devices with which middle school students can explore scientific ideas using GoGo Board and NetLogo that connect real and simulated worlds. Related research literature was reviewed to design a simulation-based learning model using computer simulation and robot-related activities. In order to construct devices for exploratory experiments, GoGo Board was adopted for developing the interface of Micro-Based Laboratory(MBL) devices with several sensors while NetLogo was used for connecting MBL devices (real world) and simulated experiments (virtual world). The simulation contents were developed in the area of heat equilibrium for changing temperature and the conduct-current relationship appeared in the textbook of middle school science class. With the developed device and contents students can visualize the change of temperature cold and hot waters in terms of heat equilibrium. They also can measure the change of conductor representing the relationship between conductor and current. The formative evaluation of the contents carried out with several middle school students indicated the future direction for upgrading simulation contents and interface. The results might be beneficial for science educators who want to apply simulation contents with the use of computers.

• Interdisciplinary Bio Central
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• v.4 no.1
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• pp.2.1-2.7
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• 2012

Introduction: Histone deacetylases (HDAC) are a class of enzymes that remove acetyl groups from ${\varepsilon}$-N-acetyl lysine amino acids of histone proteins. Their action is opposite to that of histone acetyltransferase that adds acetyl groups to these lysines. Only few HDAC inhibitors are approved and used as anti-cancer therapeutics. Thus, discovery of new and potential HDAC inhibitors are necessary in the effective treatment of cancer. Materials and Methods: This study proposed a method using support vector machine (SVM) to classify HDAC8 inhibitors and non-inhibitors in early-phase virtual compound filtering and screening. The 100 experimentally known HDAC8 inhibitors including 52 inhibitors and 48 non-inhibitors were used in this study. A set of molecular descriptors was calculated for all compounds in the dataset using ADRIANA. Code of Molecular Networks. Different kernel functions available from SVM Tools of free support vector machine software and training and test sets of varying size were used in model generation and validation. Results and Conclusion: The best model obtained using kernel functions has shown 75% of accuracy on test set prediction. The other models have also displayed good prediction over the test set compounds. The results of this study can be used as simple and effective filters in the drug discovery process.

• Journal of The Korean Association of Information Education
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• v.20 no.6
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• pp.535-542
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• 2016

In this study, we examined the perceptions of teachers and students to utilize 3D educational content. We conducted a survey about the effect of utilizing 3D educational content, interest in the 3D content, the advantages and problems of utilizing 3D education in class by targeting at elementary school teachers and elementary school students, Surveyed are students and teachers who participated the contest for 3D content development. Research results, both teachers and students were very positive about the educational effects of 3D content and they take advantage of educational content, as well as higher interest in 3D making education. We also found that they require overall support including 3D education-relevant materials and teacher training school in the field.

• Journal of Internet Computing and Services
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• v.16 no.3
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• pp.33-41
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• 2015

In this paper, the simplification procedure of Karnaugh Map, which is essential to design digital logic circuits, was implemented as web-based educational Java applets. The learners will be able to experience interesting learning process by executing the proposed Java applets. In addition, since the proposed Java applets were designed to contain educational technologies by step-by-step procedure, the maximization of learning efficiency can be obtained. The learners can make virtual experiments on the simplification of digital logic circuits by clicking on some buttons or filling out some text fields. Furthermore, the Boolean expression and its schematic diagram occurred in the simplification process will be displayed on the separate frame so that the learners can learn effectively. The schematic diagram enables them to check out if the logic circuit is correctly connected or not. Finally, since the simplification algorithm used in the proposed Java applet is based on the modified Quine-McCluskey minimization technique, the proposed Java applets will show more encouraging result in view of learning efficiency if it is used as assistants of the on-campus offline class.

• The Journal of the Convergence on Culture Technology
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• v.4 no.3
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• pp.293-298
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• 2018

In the fourth industrial revolution era triggered by the popularization of smart phones, Human daily life and all industrial sites are becoming software and intelligent. With the universal software education for all students nationwide from 2018, Demand is surging, and hardware is interlocked using software technology and Arduino. However, expensive control boards and dozens of different electronic components have to be prepared separately and problems are occurring. In addition, if the same training is repeated, Significantly many parts are lost or destroyed. Being prepared to start a new class is also becoming a very serious problem. In this study, we implement VR technology based on virtualization technology of Arduino board and various electronic parts. In addition, 3D graphics realistic Arduino kit and various electronic components are provided in API form. In this paper, we propose a method of interworking software and virtual hardware on virtualization base.

• The KIPS Transactions:PartC
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• v.12C no.5 s.101
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• pp.709-716
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• 2005

QoS is an important requirement of the FTTH (Fiber To The Home) subscriber in access network using E-PON (Ethernet Passive Optical Network). In this research, we describe the structure of the access network and propose a bandwidth guarantee scheme for subscriber and service according to the requirements of the subscriber, service and system. This scheme uses two kinds of the classification table, which are called 'service classification table' and 'subscriber classification table.' Using the classification table, we can identify the flow of the subscriber and service. Also, we compute the number of hash table entry to minimize the loss ratio of flows using the M/G/k/k queueing model. Finally, we apply the DRR scheduling through virtual queueing per subscriber instead of the aggregated class.

• The KIPS Transactions:PartC
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• v.12C no.5 s.101
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• pp.679-686
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• 2005

Because EPON access network shares a medium and aggregates the traffic from EPON subscribers, scheduling media access control on EPON bandwidth allocation is very important. Furthermore DBA mechanism of EPON based on TDMA is out of specification and up to implementation. This paper deals with a DBA method to guarantee the QoS of the delay sensitive traffic on the base of best-effort service and delay priority queue management. The proposed method performs virtual scheduling algorithm for the integrated traffic. It uses the same MAC messages and tries to guarantee the QoS of higher priority traffic first with a simple DBA architecture. We evaluate the algorithm for traffic delay according to polling interval and traffic load of upstream and downstream. The results show that the proposed method can guarantee the QoS of the delay sensitive traffic with priority of the service classes.