• Journal of the Korean Institute of Telematics and Electronics S
• /
• v.35S no.2
• /
• pp.1-9
• /
• 1998

ATM was adopted as the switching and multiplexing technique for BISDN which aims at transmitting traffics with various characteristics in a unified network. To construct these ATM networks, the most important aspect is the design of the switching system with high performance and different service capabilities. In this paepr, we analyze the performance of an input and output queueing switch with preemptive priority which is considered to be most suitable for ATM networks. For the analysis of an input queue, we model each input queue as two separate virtual input queues for each priority class and we approximage them asindependent Geom/Geom/1 queues. And we model a virtual HOL queue which consists of HOL cells of all virtual input queues which have the same output address to obtain the mean service time at each virtual input queue. For the analysis of an output quque, we obtain approximately the arrival process into the output queue from the state of the virtual HOL queue. We use a Markov chain method to analyze these two models and obtain the maximum throughput of the switch and the mean queueing delay of cells. and analysis results are compared with simulation to verify that out model yields accurate results.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.45 no.2
• /
• pp.55-60
• /
• 2008

Packet-switched wavelength division multiplexing (WDM) ring networks have been extensively studied as solutions to the increasing amount of traffic in metropolitan area networks, which is widely expected to be a mix of unicast and multicast traffic. In this paper we study the fairness between unicasting and multicasting in slotted packet-switched WDM ring networks that employ a tunable transmitter and fixed tuned receiver at each node and a posteriori buffer selection. We find that single-step longest queue selection algorithm generally results in unfairness between unicasting and multicasting or a lilted relative priority for multicast vs. unicast traffic. We present the various virtual output queue structures and their performance.

• Proceedings of the IEEK Conference
• /
• 2002.06a
• /
• pp.347-350
• /
• 2002

In the input buffer switch system, VOQ(Virtual Output Queue) archives 100% throughput. The VOQ with the systolic architecture maintains an uniform performance regardless of a number of Packet class and output port, so that it doesn't have a limitation of scalability. In spite of these advantages, the systolic architecture VOQ is difficult to change sorting order In this paper, we Proposed a systolic architecture VOQ which support weighted round robin(WRR) algorithm to provide with flow control service.

• Proceedings of the IEEK Conference
• /
• 2000.11a
• /
• pp.445-448
• /
• 2000

This paper considers a scheduling algorithm for high-speed routers, where the router has an N x N port input-queued switch and the input queues are composed of N VOQ(Virtual Output Queue)s at each input port. The major concern of the paper is on the scheduling mechanism for the router. The paper discusses the preferred levels of the performance measures and then develope a non-linear mixed integer programming. Additionally, the paper suggests a heuristic scheduling algorithm for efficient and effective switching.

• Proceedings of the IEEK Conference
• /
• 2002.07b
• /
• pp.884-887
• /
• 2002

This paper considers a scheduling problem of routers with VOQ(Virtual Output Queue)s, where the router has an N ${\times}$N port input-queued switch and each input queue is composed of N VOQs. The objective of the paper is to develope scheduling algorithms which minimize mean tardiness under a common due date. The paper characterizes the optimal solution properties. Based upon the characterization, a integer programming is formulated for the optimal solution and two optimal solution algorithms are developed for two special cases of 2 ${\times}$2 switch and N${\times}$N switch with identical traffic.

• Journal of Korean Institute of Industrial Engineers
• /
• v.25 no.2
• /
• pp.233-239
• /
• 1999

With the increase of Internet protocol (IP) packets the performance of routers became an important issue in internetworking. In this paper we examined the matching algorithm in gigabit router which has input queue with virtual output queueing. Port partitioning concept is employed to reduce the computational burden of the scheduler within a switch. The input and output ports are divided into two groups such that the matching algorithm is implemented within each input-output pair group in parallel. The matching is performed by exchanging input and output port groups at every time slot to handle all incoming traffics. Two algorithms, maximal weight matching by port partitioning (MPP) and modified maximal weight matching by port partitioning (MMPP) are presented. MMPP has the lowest delay for every packet arrival rate. The buffer size on a port is approximately 20-60 packets depending on the packet arrival rates. The throughput is illustrated to be linear to the packet arrival rate, which can be achieved under highly efficient matching algorithm.

• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.369-372
• /
• 2001

This paper presents the design of high-speed virtual output queue(VOQ) management scheme for high performance cell/packet switch, which has a serial cross bar structure. The proposed VOQ management scheme has been designed for wire-speed routing with a pipelined buffer management. It provides the tolerance of requests and grants data transmission latency between the VOQ manager and central arbiter using a new request control method that is based on a high-speed shifter. The designed VOQ manager has been implemented in a field programmable gate array chip with a 77MHz operating frequency, a 900-pin fine ball grid array package, and 16$\times$16 switch size.

• Proceedings of the Korean Information Science Society Conference
• /
• 2002.10e
• /
• pp.127-129
• /
• 2002

NP Forum에서는 다양한 밴더의 네트워크 프로세서와 스위치 패브릭간에 물리적 인터페이스를 제공하기 위해 CSIX-L1(Common Switch Interface-Level 1 )인터페이스를 표준화하였다. IBM 네트워크 프로세서는 MPLS 및 VPN, VLAN, Security, Ipv6와 같은 다양한 어플리케이션과 TBI. SMII CMII. POS bus등 다양한 가입자 인터페이스를 지원하며, L2 기 반에서 2.5Gbps 이상의 패킷 처리를 수행하기 때문에 많은 시스템에 사용된다. 그러나 IBM네트워크 프로세서는 스위치 인터페이스로 DASL인터페이스를 사용한다. 따라서 DASL인 터페이스와 CSIX-L1 인터페이스를 정합하기 위해서는 IBM UDASL칩을 이용해 DASL인 터페이스를 UTOPIA-L3인터페이스로 변환해야 하며, 이것을 다시 CSIX-L1인터페이스로 변환해야 한다. 따라서 본 논문에서는 UTOPIA-L3인터페이스 패킷과 CSIX-L1인터페이스 프레임을 상호 변환하는 모듈을 설계하였으며, 32비트 데이터 버스와 최대 125MHz로클록을 사용해 최대 4Gbps의 패킷처리를 제공하도록 구현하였다. 또한 스위치 패브릭의 특정 포트에서 과잉 트래픽 전달로 인해 발생할 수 있는 블로킹을 방지하기 위해 네트워크 프로세서에게 3개의 Priority／최대 64개 포트수의 VOQ(Virtual Output Queue)를 제공하는 기법에 대해서 기술한다.

• Journal of the Institute of Convergence Signal Processing
• /
• v.7 no.3
• /
• pp.136-142
• /
• 2006

Existing buffer management schemes for shared-memory output queueing switches can be classified into two types: In the first type, some constant amount of memory space is guaranteed to each virtual queue using static queue thresholds. The static threshold method (ST) belongs to this type. On the other hand, the second type of approach tries to maximize the buffer utilization in 머 locating buffer memories. The complete sharing (CS) method is classified into this type. In the case of CS, it is very hard to protect regular traffic from mis-behaving traffic flows while in the case of ST the thresholds can not be adjusted according to varying traffic conditions. In this paper, we propose a new buffer management method called weighted dynamic thresholds (WDT) which can process packet flows based on loss priorities for quality-of-service (QoS) functionalities with fairly high memory utilization factors. We verified the performance of the proposed scheme through computer simulations.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2002.05a
• /
• pp.264-267
• /
• 2002

This paper presents the design of a pipelined virtual output queue routing engine for an advanced input-queued ATM switch, which has a serial cross bar structure. The proposed routing engine has been designed for wire-speed routing with a pipelined buffer management. It provides the tolerance of requests and grants data transmission latency between the routing engine and central arbiter using a new request control method that is based on a high-speed shifter. The designed routing engine has been implemented in a field programmable gate array (FPGA) chip with a 77MHz operating frequency, 16$\times$16 switch size, and 2.5Gbps/port speed.