Systolic Architecture Vitrual Output Queue with Weighted Round Robin Algorithm

WRR 알고리즘 지원 시스톨릭 구조 가상 출력 큐

In the input buffer switch system, VOQ(Virtual Output Queue) archives 100% throughput. The VOQ with the systolic architecture maintains an uniform performance regardless of a number of Packet class and output port, so that it doesn't have a limitation of scalability. In spite of these advantages, the systolic architecture VOQ is difficult to change sorting order In this paper, we Proposed a systolic architecture VOQ which support weighted round robin(WRR) algorithm to provide with flow control service.