• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.45-52
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• 2005

This paper presents the characterization of through hole vias on printed circuit board (PCB) through the time domain and frequency domain measurements. The time domain measurement was performed on a single via using the TDR, and the model parameters were extracted by the fitting simulation using HSPICE. The frequency domain measurement was also performed by using 2 port VNA, and the model parameters were extracted by fitting simulation with ADS. Using the ABCD matrices, the do-embedding equations were derived probing in the same plane in the VNA measurement. Based on the single via characterization, the differential via characterization was also performed by using TDR measurements. The time domain measurements were performed by using the odd mode and even mode sources in TDR module, and the Parameter values were extracted by fitting with HSPICE. Comparing measurements with simulations, the maximum calculated differences were $14\%$ for single vias and $17\%$ for differential vias.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.51-56
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• 2012

In order to fabricate through-Si-vias for thermal vias by using wet etching process, anisotropic etching behavior of Si substrate was investigated as functions of concentration and temperature of TMAH solution in this study. The etching rate of 5 wt%, 10 wt%, and 25 wt% TMAH solutions, of which temperature was maintained at $80^{\circ}C$, was $0.76{\mu}m/min$, $0.75{\mu}m/min$, and $0.30{\mu}m/min$, respectively. With changing the temperature of 10 wt% TMAH solution to $20^{\circ}C$ and $50^{\circ}C$, the etching rate was reduced to $0.067{\mu}m/min$ and $0.233{\mu}m/min$, respectively. Through-Si-vias of $500{\mu}m$-depth could be fabricated by etching a Si substrate for 5 hours in 10 wt% TMAH solution at $80^{\circ}C$ after forming same via-pattern on each side of the Si substrate.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.3
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• pp.65-71
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• 2007

For chip-stack package applications, Cu filling characteristics into trench vias of $75{\sim}10\;{\mu}m$ width and 3 mm length were investigated with variations of the electroplating current density and the speed of a rotating disc electrode (RDE). Cu filling characteristics into trench vias were improved with increasing the RDE speed. There was a Nernst relationship between half width of trench vias of Cu filling ratio higher than 95% and the minimum RDE speed, and the half width of trenches with 95% Cu filling ratio was linearly proportional to the reciprocal of root of the minimum RED speed.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.57-63
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• 2006

For chip-stack package applications, Cu filling characteristics into trench vias of $75{\sim}10\;{\mu}m$ width and 3 mm length were investigated with variations of electroplating current density and current mode. At $1.25mA/cm^{2}$ of DC mode, Cu filling ratio higher than 95% was obtained for trench vias of $75{\sim}35{\mu}m$ width. When electroplated at DC $2.5mA/cm^{2}$, Cu filling ratios became inferior to those processed at DC $1.25mA/cm^{2}$. Pulse current mode exhibited Cu filling characteristics superior to DC current mode.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.2
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• pp.123-127
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• 2009

In order to get more higher integration density of devices, it is getting to be used more and more micro via interconnection lines for interconnecting layers or devices. However, it is very important to enhance the electrical characteristic by reducing the electrical resistivity of micro via interconnection line because it affects the reliability of packaging. In this paper, Micro vias were patterned with a diameter from 10 to 100 um by increasing the step of 10 um and 100 um height and were fabricated by micromachining technology to investigate the electrical characteristic of micro via interconnection lines. These micro vias were filled with copper by electroplating process with appling pulse current mode. And the electrical characteristics of micro via interconnection lines were measured. The measured value of electrical resistivity shows with a range from 20 to $26\;m{\Omega}$. This value from micro via interconnection lines fabricated by pulse current mode electroplating process shows better result than the resistivity from than micro via interconnection lines fabricated by DC mode ($31\;m{\Omega}$).

• KIEE International Transactions on Electrophysics and Applications
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• v.5C no.2
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• pp.81-85
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• 2005

This paper presents some interesting results regarding the harmonic performance on the photonic band-gap (PBG) structures formed by periodic conducting vias. Study on PBG structures has been one of the major topics in electromagnetics, microelectronics, and communications areas. In most of the studies, the band-gap filtering behavior was fulfilled by a periodic pattern of perforations on the ground planes of microstrip lines. Nevertheless, the PBG characteristics can also be realized using a periodic via-pattern along the transmission-line circuits. Hence, some of the via-typed PBG structures are studied and their frequency characteristics in terms of the scattering parameters are presented. It is found that by varying the length of vias with respect to the period pattern, different harmonic performances are observed.

• Journal of the Korean institute of surface engineering
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• v.46 no.4
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• pp.158-161
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• 2013

Recently, the weight reduction and miniaturization of the electronics have placed great emphasis. The miniaturization of PCB (Printed Circuit Board) as main component among the electronic components has also become progressed. The use of acid copper plating process for Via-Filling effectively forms interlayer connection in build-up PCBs with high-density interconnections. However, in the case of copper-via filled in a bath, which is greatly dependent on the effects of additives. This paper discusses effects of Cl ion on the filling of PCB vias with electrodeposited copper based on both electrochemical experiment and practical observation of cross sections of vias.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.11
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• pp.874-878
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• 2001

Solder bump was electroplated on wafer for flip chip application. The process is as follows. Ti/Cu were sputtered and thick PR was formed by several coating PR layer. Fine pitch vias were opened using via mask and then Cu stud and solder bump were electroplated. Finally solder bump was formed by reflow process. In this paper, we opened 40㎛ vias on 57㎛ thick PR layer and electroplated solder bump with 70㎛ height and 40㎛ diameter. After reflow process, we could form solder bump with 53㎛ height and 43㎛ diameter. In plating process, we improved the plating uniformity within 3% by using ring contact instead of conventional multi-point contact.

• Proceedings of the Materials Research Society of Korea Conference
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• 2008.11a
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• pp.28.2-28.2
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• 2008

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.05a
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• pp.659-660
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• 2010