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Study on the Electric Characteristics of Electroplated Micro Vias with Current Mode

전류모드에 따른 전해도금된 마이크로 비아의 전기적 특성 연구

  • Published : 2009.02.01

Abstract

In order to get more higher integration density of devices, it is getting to be used more and more micro via interconnection lines for interconnecting layers or devices. However, it is very important to enhance the electrical characteristic by reducing the electrical resistivity of micro via interconnection line because it affects the reliability of packaging. In this paper, Micro vias were patterned with a diameter from 10 to 100 um by increasing the step of 10 um and 100 um height and were fabricated by micromachining technology to investigate the electrical characteristic of micro via interconnection lines. These micro vias were filled with copper by electroplating process with appling pulse current mode. And the electrical characteristics of micro via interconnection lines were measured. The measured value of electrical resistivity shows with a range from 20 to $26\;m{\Omega}$. This value from micro via interconnection lines fabricated by pulse current mode electroplating process shows better result than the resistivity from than micro via interconnection lines fabricated by DC mode ($31\;m{\Omega}$).

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References

  1. S. F. Al-Sarawi, D. Aboott, and P. D. Franzon, 'A review of 3-D packaging technology', IEEE Trans. on Comp. Packag. Manufact. Technol., Vol. 21, No. 1, p. 2, 1988 https://doi.org/10.1109/96.659500
  2. 주철원, 임성훈, 한병성,'감광성 BCB를 이용한 절연막층에서의 비아형성', 전기전자재료학회논문지, 14권, 5호, p. 351, 2001
  3. 이영민,'광소자 패키징 기술', 전기전자재료, 16권, 8호, p. 10, 2003
  4. M. Hirano, K. Nishikawa, I. Toyoda, S. Aoyama, S. Sugitani, and K, Tamassaki, 'Three-dimensional interconnect technology for ultra-compact MMICs', Solid-state Elecro., Vol. 41, No. 10, p. 1451, 1997 https://doi.org/10.1016/S0038-1101(97)00088-9
  5. 신용덕, 조인철,'세라믹 다층 기능 패키지', 전기전자재료, 13권, 7호, p. 14, 2000
  6. R. Crowley, 'Three-dimensional electronics packaging', Tech. Rep. Tech Search Int. Inc. Austin, p. 7, 1995
  7. K. Takahashi, T. Yoshihiro, Y. Yasuhiro, H. Masataka, S, Tomotoshi, M. Tadahiro, S. Masahiro, and B, Manabu, 'Current status of research and development for three- dimensional and chip stack technology', Jpn. J. Appl. Phys., Vol. 40, p. 3031, 2001 https://doi.org/10.1143/JJAP.40.3032
  8. P. Ramm, 'Three-dimensional metallization for vertically integrated circuits', Microelectron. Eng., Vol. 37, p. 39, 1997 https://doi.org/10.1016/S0167-9317(97)00092-0
  9. C. H. Seah, S. Mridha, and L. H Chan, 'DC/pulse plating of copper for trench/via filling', J. Mater. Process. Technol., Vol. 114, p. 233, 2001 https://doi.org/10.1016/S0924-0136(01)00614-8
  10. T. Kobayashi, H, Kawasaki, K. Mihara, and H. Honma, 'Via-filling using electroplating for build-up PCBs', Electrochimica Acta, Vol. 47, p. 85, 2001 https://doi.org/10.1016/S0013-4686(01)00592-8
  11. D. Varadarajan, C. Y. Lee, and W. N. Gill, 'A tertiary current onto high aspect ratio sub-0.25 $\mu$m trenches', J Electrchem. Soc., Vol. 147, p. 3382, 2000 https://doi.org/10.1149/1.1393910