• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 학술대회 논문집 정보 및 제어부문
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• pp.165-168
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• 2008

The experimental results of exposing IGBT (Insulated Gate Bipolar Transistor) samples to gamma radiation source show shifting of threshold voltages in the MOSFET and degradation of carrier mobility and current gains. At low total dose rate, the shift of threshold voltage is the major contribution of current increases, but for more than some total dose, the current is increased because of the current gain degradation occurred in the vertical PNP at the output of the IGBTs. In the paper, the collector current characteristics as a function of gate emitter voltage (VGE) curves are tested and analyzed with the model considering the radiation damage on the devices for gate bias and different dose. In addition, the model parameters between simulations and experiments are found and studied.

• 전자공학회지
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• 제24권6호
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• pp.38-49
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• 1997

0.4mm Resign Rule의 Super Low Power Dissipation, Low Voltage. Operation-5- Full CMOS SRAM Cell을 개발하였다. Retrograde Well과 PSL(Poly Spacer LOCOS) Isolation 공정을 사용하여 1.76mm의 n+/p+ Isolation을 구현하였으며 Ti/TiN Local Interconnection을 사용하여 Polycide수준의 Rs와 작은 Contact저항을 확보하였다. p-well내의 Boron이 Field oxide에 침적되어 n+/n-well Isolation이 취약해짐을 Simulation을 통해 확인할 수 있었으며, 기생 Lateral NPN Bipolar Transistor의 Latch Up 특성이 취약해 지는 n+/n-wellslze는 0.57mm이고, 기생 Vertical PNP Bipolar Transistor는 p+/p-well size 0.52mm까지 안정적인 Current Gain을 유지함을 알 수 있었다. Ti/TiN Local Interconnection의 Rs를 Polycide 수준으로 낮추는 것은 TiN deco시 Power를 증가시키고 Pressure를 감소시킴으로써 실현할 수 있었다. Static Noise Margin분석을 통해 Vcc 0.6V에서도 Cell의 동작 Margin이 있음을 확인할 수 있었으며, Load Device의 큰 전류로 Soft Error를 개선할수 있었다. 본 공정으로 제조한 1M Full CMOS SRAM에서 Low Vcc margin 1.0V, Stand-by current 1mA이하(Vcc=3.7V, 85℃기준) 를 얻을 수 있었다.

• 폴리머
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• 제30권3호
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• pp.253-258
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• 2006

4 종류의 n형 유기 반도체 물질 F16CuPC, NTCDA, PTCDA, PTCDI C-8을 사용하여 ITO/n형 활성물질/Al gate/n형 활성물질/Al으로 구성되는 세로형 유기 박막트랜지스터를 제작하였다. 캐리어 이동도의 차이를 갖는 유기 물질의 종류와 유기 박막층의 두께 조절에 따른 유기 박막트랜지스터의 전류전압(I-V) 특성 및 전류의 온오프비에 미치는 영향을 조사하였다. PTCDI C-8을 사용한 세로형 유기 박막트랜지스터에서 낮은 구동전압과 높은 스위칭 특성을 보였다. ITO/PEDOT-PSS/P3HT/F16CuPc/Al gate/F16CuPc/Al으로 구성되는 발광트랜지스터를 제작하였고, 20 V에서 최고 0.054의 양자 효율을 나타내었다.

• 한국정보통신학회논문지
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• 제21권9호
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• pp.1627-1634
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• 2017

비정질 InGaZnO 박막 두께가 다른 무접합 트랜지스터를 제작하고 두께에 따른 양과 음의 게이트 스트레스 전압 및 빛을 비춘 상태에서 소자 불안정성을 분석하였다. 채널 박막 두께가 얇을수록 게이트 스트레스 및 빛이 인가된 상태에서 문턱전압 및 드레인 전류 변화가 큰 것을 알 수 있었다. 그 원인을 stretched-exponential 모델과 소자 시뮬레이션을 수행하여 설명하였다. 박막이 얇을수록 캐리어 트랩핑 시간이 짧기 때문에 전자나 홀이 빨리 활성화되는 것과 채널 박막의 뒷부분에서 채널의 수직 전계가 증가하여 전자나 홀을 많이 축적할 수 있는 것으로 설명하였다. IGZO 무접합 트랜지스터 제작에서 채널 박막의 두께를 결정할 때 채널 박막 두께가 얇을수록 소자 불안정성이 큰 것을 고려해야 됨을 알 수 있다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.271-276
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• 2017

The triple-gate tunnel FETs encapsulated with an epitaxial layer (EL TFETs) is proposed to lower the subthreshold swing of the TFETs. Furthermore, the band-to-band tunneling based on the maximum electric-field can occur thanks to the epitaxial layer wrapping the Si fin. The performance and mechanism of the EL TFETs are compared with the previously proposed TFET based on simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권1호
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• pp.41-45
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• 2012

We observed that in chemical vapor deposition (CVD) tungsten silicide (WSix) poly gate scheme, the gate oxide thickness decreases as gate length is reduced, and it intensifies the roll-off properties of transistor. This is because the fluorine diffuses laterally from WSix to the gate sidewall oxide in addition to its vertical diffusion to the gate oxide during gate re-oxidation process. When the channel length is very small, the gate oxide thickness is further reduced due to a relative increase of the lateral diffusion than the vertical diffusion. In DRAM cells where the channel length is extremely small, we found the thinned gate oxide is a main cause of poor retention time.

• Journal of Information Display
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• 제1권1호
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• pp.3-8
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• 2000

We have developed a high performance vertical alignment TFT-LCD (Thin Film Transistor Liquid Crystal Display), that shows a high light transmittance, and wide viewing angle characteristics with an unusually high contrast ratio. In order to optimize the electro-optical properties we have studied the effect of cell parameters, multi-domain structure and retardation film compensation. With the optimized cell parameters and process conditions, we have achieved a 24" wide UXGA TFTLCD monitor (16:10 aspect ratio 1920X1200) showing a contrast ratio of over 500:1, panel transmittance near 4.5%, response time near 25 ms, and viewing angle higher than 80 degree in all directions.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.II
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• pp.1440-1442
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• 2005

We have fabricated vertical type organic thin film transistors (OTFTs) using organic semiconductor materials such as F16CuPc, NTCDA, PTCDI C-8 and C60. The layers of OTFT were fabricated by vacuum evaporation technique and spin casting method onto the Indium Tin Oxide (ITO) coated glass. I-V characteristics and on-off ratios of the fabricated OTFTs were investigated. In addition, we have fabricated light emitting transistor using MEH-PPV and then investigated EL electroluminescent properties.

• Current Applied Physics
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• 제18권11호
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• pp.1415-1421
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• 2018

Unlike ordinary organic field-effect transistors (OFETs), saturation current is hardly to be found in vertical OFETs (VOFETs). Moreover, the fabrication process of patterned sourced for VOFETs is quite complex. In this current work, a simple solution processed VOFET with directly deposited intermediate silver source electrode has been demonstrated. The VOFET exhibits a high leakage current that induces an inversion polarity of its transistor behavior. Interestingly, a well-defined saturation current was observed in the linear scale of transfer characteristic. The VOFET operated with high-current density > $280mA/cm^2$ at $V_d=5V$. Overview potential of the fabricated device in display application is also presented. This preliminary work does open-up a new direction in VOFET fabrication and their application.

• 대한전자공학회논문지
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• 제23권6호
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• pp.773-779
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• 1986

In this paper, we discuss fabrication and characteristics of the Vertical Double diffused MOS(VDMOS) transistor. The epi layers of starting wafers are 18~22\ulcorner in thickness and 8~12\ulcornercm in resistivity. The channel regions are defined through the self-aligned double diffusion process. The characteristics of the fabricated VDMOS are breakdown voltage of 240V, threshold voltage of 2V, on-resistance of 226\ulcornerand transconductance of 3x10**-3 mho.