JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Fluorine Effects on NMOS Characteristics and DRAM Refresh

  • Choi, Deuk-Sung (Yeoungnam College of Science and Technology - Electronics and Information)
  • Received : 2011.09.22
  • Published : 2012.03.31
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Abstract

We observed that in chemical vapor deposition (CVD) tungsten silicide (WSix) poly gate scheme, the gate oxide thickness decreases as gate length is reduced, and it intensifies the roll-off properties of transistor. This is because the fluorine diffuses laterally from WSix to the gate sidewall oxide in addition to its vertical diffusion to the gate oxide during gate re-oxidation process. When the channel length is very small, the gate oxide thickness is further reduced due to a relative increase of the lateral diffusion than the vertical diffusion. In DRAM cells where the channel length is extremely small, we found the thinned gate oxide is a main cause of poor retention time.

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References

  1. C. H. Kao, C. S. Lai and C. L. Lee, "Electrical and reliability improvement in Polyoxide by fluorine implantation," Journal of Electorchem. Soc., Vol.154, Issue4, pp.H259-H262, Feb., 2007. https://doi.org/10.1149/1.2433471
  2. Y. Mitani, H. Satake, Y. Nakasaki and A. Toriumi, "Improvement of charge-to-breakdown distribution by fluorine incorporation into thin gate oxides," Electron Devices, IEEE Transactions on, Vol.50, No.11, pp.2221-2226, Nov., 2003. https://doi.org/10.1109/TED.2003.818152
  3. J. C. Lee, Y. P. Kim, Zulkarnain, S. J. Lee, S. W. Lee, S. B. Kang, S. Y. Choi and Y. Roh, "Study on electrical characteristics and reliability of fluorinated $HfO_{2}$ for HKMG," Micorelectronic Engineering, Vol.88, pp.1417-1420, Mar., 2011. https://doi.org/10.1016/j.mee.2011.03.033
  4. H. H. Tseng, P. J. Tobin, S. Kalpat, J. K. Schaeffer, M. E. Ramon, L. R. C. Fonseca, Z. X. Jiang, R. I. Hegde, D. H. Triyoso and S. Semavedam, "Defect passivation with fluorine and interface engineering for Hf-Based High-k/Metal gate stack device reliability and performance enhancement," Electron Devices, IEEE Transactions on, Vol.54, No.12, pp.3267-3275, Dec., 2007. https://doi.org/10.1109/TED.2007.908897
  5. W. C. Wu, C. S. Lai, J. C. Wang, J. H. Chen, M. W. Ma and T. S. Chao, "High-performance HfO2 gate dielectrics fluorinated by postdeposition CF4 plasma treatment," Journal of Electorchem. Soc., Vol.154, Issue7, pp.H561-H565, May, 2007. https://doi.org/10.1149/1.2733873
  6. P. J. Wright and K. C. Saraswat, "The effect of fluorine in silicon dioxide gate dielectrics," Electron Devices, IEEE Transactions on, Vol.36, No.5, pp.879-889, May, 1989 https://doi.org/10.1109/16.299669
  7. D. G. Lin, T. A. Rost, H. S. Lee, D. Y. Lin, A. J. Tsao and B. McKee, "The Effect of Fluorine on MOSFET channel length," Electron Device Letters, IEEE, Vol.14, No.10, pp.469-471, Oct., 1993. https://doi.org/10.1109/55.244733
  8. Y. S. Kim, K. Y. Lim, M. G. Sung, et al, "Low Resistive Tungsten Dual Polymetal gate Process for High Speed and High Density Memory Devices," Solid State Device Research Conference, 2007. ESSDERC 2007, 11-15, pp. 259-262, Sept., 2007.
  9. Y. H. S. Kim, S. D. Lee, S. M. Lee, I. S. Yeo and S. K. Lee, "Low resistive tungsten dual polymetal gate process for high speed and high density memory devices ," Electrochemical and Solid-State Letters, Vol.2, No.2, pp.88-90, Nov., 1998. https://doi.org/10.1149/1.1390744

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